Si/GaAs heterostructures fabricated by direct wafer bonding
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Si/GaAs heterostructures fabricated by direct wafer bonding Viorel Dragoi, Marin Alexe, Manfred Reiche, Ionut Radu, Erich Thallner1, Christian Schaefer1 and Paul Lindner1 Max Planck Institute of Microstructure Physics, Weinberg 2, D-06120 Halle (Saale), Germany 1 EV Group, St. Florian, A-4780 Schärding, Austria ABSTRACT Si/GaAs heterostructures were obtained by a low temperature direct wafer bonding (DWB) method which uses spin-on glass (SOG) intermediate layers. The use of intermediate SOG layers allows the fabrication of Si/GaAs heterostructures at processing temperatures lower than 200°C. The achieved bonding energy permits thinning down to a few microns of Si and GaAs wafers, respectively, using grinding procedures followed by chemical mechanical polishing (CMP). After thinning, the heterostructures sustained annealing temperatures of 450°C without damaging of the bonded interface. The above bonding procedure was successfully applied for bonding GaAs wafers to Si wafers with structured surfaces. A technology was developed based on this bonding method for producing universal GaAs-on-Si or Si-on-GaAs substrates.
INTRODUCTION Monolithic integration of compound semiconductors into silicon technology would result in new applications in optoelectronics, microwave electronics, and high temperature electronics. A specific interest is focused on the fabrication of Si/III-V compound semiconductor heterostructures. The combination of high performance III-V compound semiconductor optoelectronic devices with the charge handling functionality of modern silicon circuitry would enable the fabrication of monolithically integrated optical interconnects which will increase considerably the speed of data processing and transmission [1]. Silicon is also an ideal supporting material for GaAs and other III-V compound semiconductors due to its superior mechanical strength, low weight, and high thermal conductivity [2]. Classical thin film deposition techniques like low temperature epitaxy, metalorganic chemical vapour deposition or molecular beam epitaxy were used for the fabrication of GaAs layers on Si substrates. Compared to bulk GaAs, GaAs thin films on Si substrate suffer from two major problems: i) the presence of high dislocation densities due to the 4.1 % lattice mismatch between Si and GaAs (typical 106 ÷ 108 cm-2, instead of 103 cm-2, which is desired for device fabrication), and ii) the biaxial tensile stress generated in the plane of GaAs film during cooling from the deposition temperature due to the thermal mismatch (thermal expansion coefficient TEC - of GaAs is almost double than the TEC for Si) [3]. Direct wafer bonding (DWB) can be a valuable solution for solving the lattice mismatch problem as long as this technique impose conditions only to the flatness, microroughness and the cleanliness of the surfaces and is not depending on the crystalline properties of the two materials. Thermal mismatch remains also an issue for DWB but in the last years low temperature bonding techniques were developed (vacuum bonding [4], pl
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