Silicon Epitaxial Regrowth Passivation of SiGe Nanostructures Pattered by AFM Oxidation
- PDF / 74,211 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 6 Downloads / 195 Views
E14.5.1
Silicon Epitaxial Regrowth Passivation of SiGe Nanostructures Pattered by AFM Oxidation Xiang-Zheng Bo, Leonid P. Rokhinson, and J. C. Sturm Center for Photonics and Opto-Electronic Materials, Department of Electrical Engineering Princeton University, Princeton, NJ 08544, USA, Email: [email protected]
ABSTRACT SiGe quantum devices were demonstrated by AFM oxidation and selective wet etching with features size down to 50 nm. To passivate the devices and eliminate the interface states between Si/SiO2, low temperature regrowth of epitaxial silicon over strained SiGe has been tested. The silicon regrowth on Si0.8Ge0.2 was done by rapid thermal chemical vapor deposition (RTCVD) at 700 ºC using a hydrogen pre-cleaning process at 800 ºC and 10 torr. SIMS analysis and photoluminescence (PL) of strained SiGe capped with epitaxial regrown silicon show a clean interface. Nano-gaps between doped SiGe filled and overgrown with epitaxial silicon show an electrical insulating property at 4.2 K. INTRODUCTION Si/SiGe heterostructures attract much interest in past due to their higher carrier transport mobility than that in Si MOSFETs [1-2]. Nanodevices on Si/SiGe are of growing interest. SiGe quantum dot devices may provide a physical route to achieve quantum computing [3-4]. However, how to fabricate a quantum dot with free from interface states is still a great challenge. Silicon quantum dots with MOSFET structures suffer from the interface states between Si (channel) and SiO2 (gate oxide) [5]. Epitaxially grown strained SiGe on silicon can have a defect-free interface with atomic correspondence. Transport carriers can be confined by band offsets at Si/SiGe heterojunctions. The goal of our work is to apply them to fabricate “clean” quantum dot devices. In this paper, we first show that SiGe quantum dots can be fabricated by AFM oxidation and selective wet etching. We then test the epitaxial regrowth of Si on strained SiGe to passivate the device with a maximum process temperature ≤ 800 °C, showing a “clean” interface. b
a 2 nm Si Cap 2 nm i-Si0.7Ge0.3 +
8 nm p -Si0.7Ge0.3 2 nm i-Si0.7Ge0.3 Si Substrate
SiO2
c
d
Si Cap 2 nm i-Si0.7Ge0.3 8 nm p+-Si0.7Ge0.3
Si Cap 2 nm i-Si0.7Ge0.3 8 nm p+-Si0.7Ge0.3
Si Cap i-Si0.7Ge0.3 p+-Si0.7Ge0.3
2 nm i-Si0.7Ge0.3
2 nm i-Si0.7Ge0.3
i-Si0.7Ge0.3
Si Substrate
Si Substrate
Si Substrate
Figure 1. Process to pattern Si/SiGe nanostructures: (a) Layer structure; (b) Si cap AFM oxidation; (c) HF dip to remove SiO2; (d) selective wet etching to pattern SiGe.
E14.5.2
NANOPATTERING OF Si/SiGe BY AFM OXIDATION Semiconductor nanodevices are usually patterned by electron-beam lithography and reactive-ion etching. However, these high-energy processes may induce defects which could affect nano-devices. AFM local oxidation with bias voltages smaller than 30 volts on AFM tip is a low-energy process and has a minimum feature width smaller than 20 nm on strained SiGe [67]. The maximum oxidation height on Si and SiGe is less than 3 nm, which means that layers with thickness greater 3 nm ca
Data Loading...
