Silicon-on-lnsulator Technology
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Silicon-on-lnsulator Technology Jean-Pierre Colinge and Robert W. Bower, Guest Editors Silicon-on-lnsulator (SOI) technology has been around since the 1960s when so-called silicon on sapphire (SOS) was first introduced. Silicon on sapphire has been used for many years for the fabrication of spaceborne and high-speed integrated circuits. It is still used in the fabrication of radio-frequency circuits. More recent SOI materials involve only silicon and silicon dioxide—the two most common materials used in the fabrication of integrated circuits—as opposed to SOS, which requires the use of an alumina substrate. Silicon-on-insulator technology has
Robert W. Bower, Guest Editor for this issue of MRS Bulletin, received his AB degree in physics from the University of California—Berkeley, and MSEE and PhD degrees in applied physics from The California Institute of Technology. He has worked in industry in a number of capacities including that of engineer, scientist, department head, division manager, president, and chief executive officer of various companies. He has served the last 11 years as a university professor at the University of California. Bower has published more than 70 journal and conference papers, has 24 U.S. patents, and is the author of chapters in three books. Bower's past research has been in metal-oxide-semicon-
been used for a long time in niche applications such as spacecraft electronics and devices operating in a hightemperature or radiative environment. Recently however much attention has been paid to SOI technology because it is extremely suitable for the fabrication of low-voltage integrated circuits. Such circuits are in high demand for all kinds of portable systems, ranging from cellular phones to laptop computers. In August of 1998, IBM, Sharp, and other semiconductor manufacturers announced the development of SOI chips for high-speed computing and telecommunication con-
ductor-field-effecttransistor (MOSFET) and charge-coupleddevice technology as well as in ion implantation and silicide formation and analysis. Currently he focuses his research activities on various aspects of wafer bonding and formation of three-dimensional integrated nanostructures and silicon-oninsulator. Honors and awards include membership in the National Inventors Hall of Fame for the invention of the self-aligned-gate MOSFET, the Ronald H. Brown American Innovator Award from the Commerce Department of the U.S. Government, and fellowship in the Institute of Electrical and Electronics Engineers "for inventing the self-assigned-gate ion-
MRS BULLETIN/DECEMBER 1998
implanted MOSFET and for establishing ion implantation to fabricate semiconductor integrated circuits." Bower can be reached at the Department of Electrical and Computer Engineering, University of California—Davis, Davis, CA 95616, USA; phone 530-758-6927; fax 530752-8428; e-mail bower® ece.ucdavis.edu. Jean-Pierre Colinge, Guest Editor for this issue of MRS Bulletin, received a BS degree in philosophy, an electrical engineering degree, and a PhD degree in appl
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