Simulation of capacitorless dynamic random access memory based on junctionless FinFETs using grain boundary of polycryst
- PDF / 3,374,566 Bytes
- 10 Pages / 595.276 x 790.866 pts Page_size
- 63 Downloads / 160 Views
Simulation of capacitorless dynamic random access memory based on junctionless FinFETs using grain boundary of polycrystalline silicon Min Su Cho1 · Hye Jin Mun1 · Sang Ho Lee1 · Jaewon Jang1 · Jin‑Hyuk Bae1 · In Man Kang1 Received: 26 June 2020 / Accepted: 3 November 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract In this paper, we report a junctionless FinFET-based capacitor less dynamic memory by using three-dimensional technology computer-aided design simulations. To realize the 1T-DRAM, the proposed device has been designed as a structure in which a poly-si layer is deposited on the fins of a typical junctionless FinFET. Poly-si has one or more grain boundaries (GB). A GB contains multiple traps, and these traps generally degrade device performance. Also, when poly-si is grown and utilized in semiconductor devices, non-uniform GB is formed across the entire wafer. Therefore, devices manufactured using poly-si have different GBs for each device and the performance of devices fabricated on the same wafer is different. Therefore, it is essential to design a device that can operate normally regardless of GB. The 1T-DRAM proposed in this study was simulated with the existence of GB and the direction of GB differently. Finally, a device that operates normal memory regardless of GB was designed. According to the simulation results, the retention time of the proposed 1T-DRAM has a margin of more than 10 uA/um and a retention time of more than 64 ms, regardless of the presence or absence of GBs. Keywords Capacitorless · FinFET · Grain boundary · Junctionless · Polycrystalline silicon · 1T-DRAM
1 Introduction Dynamic random access memory (DRAM) provides both a higher level of integration than SRAM and, generally, a higher operating speed than that of non-volatile memory, which consists of one transistor and one capacitor. However, the downscaling of metal–oxide–semiconductor field effect transistors is essential for miniaturizing the dimensions of DRAM storage capacitors. To maintain the capacitance required to achieve the desired sensing margin, the capacitor length must be relatively long even as its other dimensions decrease. Capacitor downscaling is very difficult, and other means are required to replace it. Therefore, DRAM devices that operate with only one transistor and without a capacitor (1T-DRAM) have been proposed and researched extensively [1–5]. Typically, 1T-DRAM executes the write operation through one of the four following means: bipolar junction transistor effect, impact ionization [6], band-to-band * In Man Kang [email protected] 1
School of Electronic and Electrical Engineering, Kyungpook National University, 80 Daehak‑ro, Buk‑gu, Daegu 41566, Republic of Korea
tunneling (BTBT) effect [7], and gate-induced drain leakage [8]. The holes stored in the storage region in these ways form an extra charge, which changes the device threshold voltage (Vth). Therefore, device current differs even under the same applied read bias. To improve the performance of a 1T-DRAM devic
Data Loading...
