Future of dynamic random-access memory as main memory
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Introduction Dynamic random-access memory (DRAM) has served as the main memory in modern computers since it was introduced by Intel Corporation in 1972. DRAM is widely used in modern computers owing to characteristics such high-speed operation, large integration density, and excellent reliability. A DRAM cell has a simple structure comprising one capacitor (1C) connected by one transistor (1T) (1T-1C) to the bit line (the line through which information is written to/ read from the memory cell) (Figure 1a). The access transistor is connected to the word line and acts as a switch. The capacitor stores each bit of data as a negative or positive electrical charge. The memory state is read by sensing the stored charge on the capacitor via the bit line, which is set to Vcc/2, (Vcc: operating voltage of the chip) with the transistor closed. When the access transistor is on, the stored charge carriers flow into the bit line, which changes its potential. This voltage change is detected and amplified by the sense amplifier connected to the bit line. During the past several decades, exponential growth in the number of memory cells per chip has occurred. Perpetual memory cell scaling has been the major strategy for realizing rapid increases in memory density.1 DRAM is amenable to scaling because of its simple structure, and scaling of DRAM down to a ∼100-nm technology node (specific manufacturing process and its design rule) is easily achieved with traditional
materials such as Si-based dielectrics (SiO2 and SiNx) and electrodes (poly-Si). This excellent scalability of DRAM has led to its long-lasting success. Today, much effort is devoted to accelerating the scaling of DRAM cells further to the ∼10-nm technology node2 (Figure 1b). DRAM is a charge-based RAM that requires a certain cell capacitance value (∼10 f F/cell) to secure the minimum voltage difference detectable by the sense amplifier, regardless of cell size. The ever-shrinking dimension of the capacitor in DRAM cells will eventually result in failure to meet this cell capacitance requirement. Hence, advancing capacitor technology is essential for continued scaling of DRAM. The scaling of the DRAM cells also raises problems in the access transistor. Without major innovations in structure, materials, and processing, scaling of DRAM will end soon.
Transistor technology in DRAM Unlike the transistor in performance-oriented logic devices, the access transistor in DRAM requires a high ON/OFF current ratio (∼108) to prevent substantial loss of the charges stored in the capacitor and to write the data within a short time (less than a few tens of a nanosecond). As the DRAM cell shrinks, obtaining sufficient data retention time becomes more challenging. The increase in the channel doping concentration with scaling of the feature size results in increased electrical field and junction leakage current. A simple and effective way
Seong Keun Kim, Center for Electronic Materials, Korea Institute of Science and Technology, South Korea; [email protected] Mihaela Popovici, Semicondu
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