Simulation of Realistic Core-shell Silicon Nanowires
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0910-A01-04
Simulation of Realistic Core-shell Silicon Nanowires Rana Biswas1, and Bicai Pan2 1 Depts. of Physics and Astronomy, Electrical and Computer Engineering, Microelectronics Research Center and Ames Lab, Iowa State University, Ames, IA, 50011 2 Dept. of Physics, University of Science and Technology of China, Hefei, 230026, China, People's Republic of ABSTRACT We have developed an efficient scheme for simulating silicon nanowires with crystalline cores and amorphous sheaths, using molecular dynamics. By starting with a crystalline nanowire and performing high temperature anneal an amorphous outer sheath can be grown with controlled thickness on the nanowire. Simulations for [001] nanowires with diameters of 12 nm find low energy facets between the amorphous and crystalline layers. Simulations for [110] nanowires find weak faceting and an inhomogeneous amorphouscrystalline boundary.
INTRODUCTION An intense scientific effort has been directed towards the synthesis and fundamental understanding of semiconductor nanowires that are expected to play a vital role in nanotechnology, chemical sensors, solar cells, and catalysis over the next decade. Nanowires have been synthesized from metallic and semiconducting materials [1-6]. Semiconducting nanowires can be made doped and hence can act as nanoscale conducting elements in emerging nano-electronics applications. Already nanometer size electronic devices such as p-n junctions, transistors, and superlattices have been synthesized from semiconducting nanowires [1-6]. The principal synthesis method for semiconductor nanowires is the vapor liquid solid (VLS) synthesis method. In this method, Au droplets on a silicon substrate act as a catalyst for vapor phase synthesis of silicon nanowires, with nanowire diameters ranging from 6-30 nm. The size of the silicon nanowires was controlled by the diameter of the Au nanoparticles on a silicon substrate. During the vapor-liquid-solid (VLS) phase synthesis a supersaturated silicon-Au alloy is formed that leads to the nucleation of the silicon nanowire. Such nanowires were found to have a crystalline silicon core surrounded by a sheath of amorphous silicon dioxide, which was 1-3 nm thick. The crystalline cores were present for nanowires as small as 2 nm in diameter. The VLS technique [1,3,5] has successfully synthesized semiconducting nanowires of various materials (e.g. Si, Ge, GaP, and ZnO). A complementary method for nanowire synthesis is the oxide-assisted growth technique[4]. Here SiO2 powders were heated to 1200 C in an alumina tube under a gas flow of hydrogen mixed in argon. Silicon nanowires were synthesized downstream on the inner tube wall. Nanowires with diameters ranging from a few nm to tens of nm were formed composed of a crystalline core surrounded by a silicon oxide sheath that had a thickness of about one-third of the nanowire diameter. A novel HF etching procedure
was utilized [4] to remove the oxide sheath and produce silicon nanowires with Hterminated surfaces. A majority of the nanowires had their axis a
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