Thermal characterization of vertical silicon nanowires
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Arrays of vertically aligned silicon wires of 250 nm–4 lm in diameter were fabricated in a top–down process using photolithography and deep reactive ion etching at cryogenic temperatures. Using the 3-omega method, thermal conductance of vertical silicon nanowires, i.e., nanopillars, was measured immediately on-chip without the need of breaking off single wires and mounting them into a special testing device. The Seebeck coefficient was measured with 2-mm2 arrays of pillars of 260 nm in diameter, which were pressure-joined with bulk chips for testing. Testing was performed in the temperature range between 50 and 470 °C at applied temperature gradients of up to 190 °C. We found a reduction of the thermal conductivity to less than 30% of the bulk silicon, confirming that arrayed vertical nanowires fabricated in an economical top–down process can strongly promote silicon as a thermoelectric material.
I. INTRODUCTION
Research on semiconductor nanowires has been dramatically increased over last two decades.1 Among a variety of fields, nanowire-based thermoelectrics has emerged, which is caused by a significant reduction of thermal conductivity j in these structures with respect to the bulk. Strong interaction of the phonons with the surface is the origin of this diameter-dependent and surface morphology– related effect, which can amount up to a two-orders-ofmagnitude reduction of j of bulk silicon.2–4 Silicon offers several advantages over the standard thermoelectric materials, Bi2Te3 and PbTe, which can be essential to overcome the present restriction of thermoelectrics to niche applications. For waste heat recovery, e.g., from combustion engines,5,6 high-temperature stability, environmental compatibility, safe medium- to long-term availability, and ongoing price reduction are mandatory, which is provided by silicon. Basic research on the thermoelectric (TE) properties of silicon nanowires is ongoing, but so far has been limited to single elements. However, nanowire-based thermoelectric generators will require a dense arrangement of nanowires in parallel to provide the necessary output power, e.g., for maintenance-free electronics or sensorics. With respect to economical fabrication of nanopillar (NP) arrays, top–down fabrication using photolithography and deep reactive ion etching (DRIE) followed by thermal oxidation have been developed, which may be preferable over bottom–up approaches based on self-assembling.7–9 For packaging into thermocouples, vertically aligned nanowires, i.e., nanopillars (NPs) of both n- and p-type doping and having uniform diameter and length, are a)
Address all correspondence to this author. e-mail: [email protected] DOI: 10.1557/jmr.2011.60 1958
J. Mater. Res., Vol. 26, No. 15, Aug 14, 2011
http://journals.cambridge.org
Downloaded: 18 Mar 2015
required. Figure 1 shows a schematic of a thermocouple comprising n- and p-doped NP arrays joined using a hightemperature-stable silver sintering process.10 The thermal properties of nanowires are conventionally measured by heating at one end and se
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