Simulation Studies of TiN PVD and CVD Thin Films for Contact/Via Liners
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CONTACT/VIA LINERS D.S. Bang, J.P. McVittie, and K.C. Saraswat Center for Integrated Systems, Stanford University, Stanford, CA 94305 J.A. lacoponi, J. Gray, and Z. Krivokapic Advanced Micro Devices, One AMD PI., Sunnyvale, CA 94088 K. A. Littau Applied Materials, 3050 Bowers Ave., Santa Clara, CA, 95054 Abstract TiN PVD and CVD models have been incorporated in the SPEEDIE topography simulator. A parameter extraction methodology is presented which allows engineers to locally calibrate their process to the SPEEDIE simulator. The calibration requires no special equipment or modifications to the PVD or CVD equipment. Parameter extraction is demonstrated with Applied Materials deposition equipment.
Introduction TiN thin films are used as diffusion barriers/seed layers for W-filled and hot-Al contacts and vias in modern Very Large Scale Integration (VLSI) circuits. Typically, TiN thin films are deposited through sputtering or Physical Vapor Deposition (PVD). However, as VLSI devices scale down in size, the contact/via height to width aspect ratio increases, which causes a decrease in TiN sidewall and bottom coverage. An alternative to PVD of TiN is Chemical Vapor Deposition (CVD) of TiN with tetrakisdimethylamino titanium (TDMAT), which exhibits enhanced sidewall and bottom coverage over conventional PVD TiN. TiN PVD and CVD models are incorporated in the SPEEDIE (Stanford Profile Emulator for Etching and Deposition in IC Engineering) simulator [1]. These models are calibrated to processes on Applied Materials deposition equipment by using overhang test structures (Fig. 1), and the calibration is verified by comparing calibrated simulations to experimental deposition for contacts. Experiment TiN PVD was performed in the Nitrided mode, i.e. nitrogen reaction at the target, with an Applied Materials sputter system onto 15 cm diameter wafers. The sputter target was 30 cm in diameter, and the target to substrate throw distance was about 5 cm. Depositions were performed at 3 mTorr and substrate temperature was 2000 C. TiN CVD was performed with an Applied Materials CVD chamber by the decomposition of TDMAT with a He carrier gas, but without NH 3 [2]. Chamber pressure was 1 Torr, substrate temperature was 4000 C, and the susceptor temperature was 470' C. The high deposition temperature was chosen to give low step coverage to test the model. Higher (>90%) step coverages are obtained at lower susceptor temperature. Scanning Electron Micrographs (SEM) were taken for VLSI structures and test structures at the wafer centers. PVD and CVD Models A deposition model is used in which the local deposition rate for a segment of a VLSI feature is proportional to the net flux arriving at that segment (Fig. 2). This model assumes 173
Mat. Res. Soc. Symp. Proc. Vol. 389 ©1995 Materials Research Society
compositionally uniform films; however, if models which do not make this assumption are used, the parameter extraction equations below can be modified accordingly. This model incorporates deposition rates which are non-linear functions of
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