Single-electron transistor: review in perspective of theory, modelling, design and fabrication
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REVIEW PAPER
Single-electron transistor: review in perspective of theory, modelling, design and fabrication Rashmit Patel1
•
Yash Agrawal2 • Rutu Parekh2
Received: 28 June 2020 / Accepted: 10 August 2020 Ó Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract Integrated circuit (IC) technology has grown tremendously over the last few decades. The prime goal has been to achieve low-power and high-performance in logic and memory devices with minimal footprint. This has lead to continuous scaling of devices and interconnects over silicon chips. Scaling of technology plays an important role for improvement of IC performance in terms of delay, signal-integrity and power-dissipation. Novel devices like FinFET, nano-electromechanical systems, graphene-FETs and single-electron transistor (SET) offer several advantages over various shortcomings of scaling. The future of IC industry is proposed to be heterogeneous 3D integration of different technologies. A SET is a potential nano device that works on quantum mechanical principle and can be co-integrated with the widely adopted complementary metal-oxide semiconductor technology to enhance its performance at scaled technology nodes. To explore the feasibility of SET, an extensive literature review has been carried out in this paper. The literature review comprises comprehensively research work related to SET theory, design and fabrication. Also, the SET based computing system design is presented for room temperature operation. The extensive literature review and thereafter execution of varying analyses reveal that the SET is a potential nano-device for futuristic applications.
1 Introduction In the present scenario, the IC designs assimilate very large scale integration (VLSI) technology as key domain. These incorporate metal oxide semiconductor field effect transistor (MOSFET) as fundamental circuit elements. A efficient VLSI design demands high-speed, high-chip density and low-power. This can be attained by scaling down the size of transistors. However, the scaling of devices concurrently leads to aggregation of several non-ideal issues such as leakage current, process variation, short-channel effects, degraded signal integrity and power dissipation & Rashmit Patel [email protected] Yash Agrawal [email protected] Rutu Parekh [email protected] 1
Space Applications Centre (ISRO) SEPD/SEG/SEDA, Ahmedabad, Gujarat, India
2
Dhirubhai Ambani Institute of Information and Communication Technology DA-IICT, Gandhinagar, Gujarat, India
(Kuhn et al. 2008; Krautschneider et al. 1997; Jacob et al. 2017). To limit these shortcomings and improvise performance, several nano-devices have been explored in Parekh 2013. One of the promising emerging devices is the singleelectron transistor (SET). The conventional MOSFET operates by virtue of charge flow between source and drain terminals that is controlled by gate voltage. The millions of charge carriers flowing through the channel during current conduction i
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