Strain measurements in s-Si/SiGe nanostructures by quantitative high-resolution electron microscopy
- PDF / 5,534,334 Bytes
- 8 Pages / 612 x 792 pts (letter) Page_size
- 21 Downloads / 140 Views
1026-C20-04
Strain measurements in s-Si/SiGe nanostructures by quantitative high-resolution electron microscopy Florian Hüe1,2, Martin Hÿtch1, Hugo Bender3, Jean-Michel Hartmann2, and Alain Claverie1 1 CEMES, CNRS, 29 rue Jeanne Marvig, Toulouse, 31055, France 2 CEA-Leti, 17 rue des Martyrs, Grenoble, 38054, France 3 IMEC, Kapeldreef 75, Leuven, 3001, Belgium ABSTRACT We have studied tensile-strained Si (s-Si) layers grown on nearly fully relaxed Si1-xGex virtual substrates (VS) by high-resolution transmission electron microscopy (HRTEM). Aberration-corrected HRTEM coupled with geometric phase analysis (GPA) provides precise strain values. Measurements and finite element method simulations lead to the conclusion that the strain state of the s-Si layer depends only on the Ge content of the VS underneath (x = 20, 30, 40 or 50%) but not on the layer thickness (between 5 and 37 nm). We have also used this technique to quantify the uniaxial compressive strain in the channel region of a p-MOSFET structure with embedded SiGe sources and drains. HRTEM together with GPA is thus shown to be a promising metrological tool for nanoelectronic devices. INTRODUCTION The incorporation of strained channel technology into high performance complementary metal oxide semiconductor (CMOS) devices has been essential in order to continue following Moore’s scaling law [1]. A well known technique for engineering strain is by growing thin, bi-axially tensily strained Si (s-Si) layers on top of virtual substrates with a slightly higher lattice parameter (e.g. Si1-xGex). Strained silicon-on-insulator (SOI) can then be fabricated by transferring the s-Si layer onto a layer of SiO2 through the SmartCut® process. Tensile strain leads to a splitting of the degeneracy of the conduction band minima in the directions resulting in reduced intervalley scattering. Electron mobility in s-Si/Si1xGex can be increased by 200% for x>20% [2] which enhances n-MOSFET performances. Furthermore, for holes, strain lowers the energy of the heavy hole and spin-orbit bands relative to the light hole band, leading to reduced intervalley scattering. For x>40% the hole mobility in s-Si can be increased by 220% [3]. The most commonly applied technique for measuring global strain in such devices is UV-Raman spectroscopy [4,5]. However, local strain measurements require the use of transmission electron microscopy (TEM) techniques. Electron diffraction is the most common mode of operation [6], either Nano Beam Diffraction (NBD) [7] or Convergent Beam Electron Diffraction (CBED) [8]. However, these techniques provide information at selected points on the specimen whereas in complex device structures it would be preferable to obtain continuous strain distributions over wide areas. We have therefore been investigating whether HRTEM can be used to map strains in strained-silicon CMOS devices. In this paper, we present results concerning strain measurements by geometric phase analysis (GPA) of HRTEM images [9]. The experimental protocol has been established by studying strained S
Data Loading...
