Strained Si-on-Insulator Fabricated from Elastically-Relaxed Si/SiGe Structures
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Strained Si-on-Insulator Fabricated from Elastically-Relaxed Si/SiGe Structures P.M. Mooney 1, G.M. Cohen 1, H. Chen 2, J.O. Chu 1, and N. Klymko 2 1 IBM T.J. Watson Research Center, Yorktown Heights, NY 10598 2 IBM Microelectronics Division, Hopewell Junction, NY 12533 ABSTRACT Blanket pseudomorphic Si0.8Ge0.2/Si layer structures grown by Rapid thermal Chemical Vapor Deposition (RTCVD) on SOI substrates were etched to form 5µm × 5µm slabs, supported by a single pedestal at the center. Symmetric tri-layer slabs, 20nm Si/236nm Si0.8Ge0.2/20nm Si supported by a SiO2 pedestal are flat and x-ray diffraction measurements of the strain and the thickness of the layers confirmed that the strain is shared between the Si and SiGe layers according to the ratio of the thickness of the SiGe and Si layers. These tri-layer structures were then firmly attached to the substrate using a filling material. A thermal oxide layer was grown on the upper and lower surface of the free-standing structures and then polycrystalline Si was deposited to fill the space between the free-standing structure and the Si substrate, thus attaching the bottom strained Si layer to the substrate. The polycrystalline Si was subsequently removed by reactive ion etching except from under the Si/SiGe/Si slab. The top SiO2 and Si layers as well as the SiGe layer were then removed selectively by wet etching. Raman spectroscopy measurements show that the strain in the attached strained Si-on-insulator layer is ε = 0.0067. INTRODUCTION The higher carrier mobility in Si under biaxial tensile strain of ~1% results in enhanced performance of field-effect transistors (FETs) fabricated in strained Si compared to devices of similar dimension fabricated in bulk Si(001) [1-5]. Strained Si layers for devices are typically achieved by growing a pseudomorphic Si layer epitaxially on a strain-relaxed SiGe buffer layer [1]. Strained-Si-on-insulator substrates have been fabricated using wafer bonding methods to transfer a thin strain-relaxed SiGe layer to form SiGe on insulator substrates on which a strained Si layer is subsequently grown epitaxially [2,3] or by a thermal mixing method [4]. Transfer of a strained Si layer by wafer bonding to form strained-Si-directly-on-insulator wafers has also been demonstrated [5,6]. With the latter structure the processing disadvantages when SiGe is present are eliminated. A serious drawback for all of these strained Si structures is the presence of defects that relieve the lattice mismatch strain in the SiGe buffer layer. The usual defects are 60o misfit dislocations that terminate in threading arms that run up to the wafer surface, thus passing through the active regions of the devices. Additionally, if the strained Si layer exceeds the critical thickness for dislocation glide, misfit dislocations may form at the interface between the strained Si layer and the SiGe buffer layer either during the growth of the strained Si layer or during subsequent device fabrication processes that are performed at higher temperatures. An alternati
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