Study and Optimization of Silicon-CVD Diamond Interface for SOD Applications
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1203-J04-01
Study and Optimization of Silicon-CVD Diamond Interface for SOD Applications Jean-Paul Mazellier1,3, Jean-Charles Arnault2, Mathieu Lions2, François Andrieu1, Robert Truche1, Bernard Previtali1, Samuel Saada2, Philippe Bergonzo2, Simon Deleonibus1, Sorin Cristoloveanu3, Olivier Faynot1 1
CEA, LETI, MINATEC, Innovative Devices Laboratory F-38054 Grenoble, France CEA, -LIST, Diamond Sensors Laboratory, F-91191 Gif-sur-Yvette, France 3 IMEP-LAHC MINATEC, F38016 Grenoble, France 2
ABSTRACT With respect to Silicon-on-Diamond approaches as an alternative to SOI where diamond is used as the buried dielectric, we have in recent works demonstrated the feasibility of a novel approaches where the CVD diamond layer is grown on silicon using Bias Enhanced Nucleation (BEN) over large area substrates, then smoothed and assembled to successfully enable the fabrication of first prototypes of silicon-on-diamond substrates. The key novelty to those SOD substrates were that only a very thin box dielectric diamond layer is used (typically from 150 to 500nm thick), as required by the current SOI technology. However we had also observed that the silicon-diamond interface quality to be sensitive to the nature of the nucleation interface. Thus the current contribution here studies the chemical nature of various capping materials used to solve the issue of electrical defects in case of direct silicon-diamond interface and at the same time to enable the whole system to benefit from the high thermal conductivity of diamond when compared to other standard electrical insulating materials. INTRODUCTION Nowadays, the semiconductor industry is facing an exciting challenge concerning its future. Not only transistor size shrinking is to be overcome but also innovative integration of new architectures and functionalities are to be managed. This advanced integration requires solutions to problems that were not addressed up to now. Thermal management at the device scale is part of this new era that needs smart solutions. Especially concerning Silicon-On-Insulator (SOI) substrates: this technology offers lots of advantages for advanced devices such as easy processing but also enhanced static and dynamic electric control. But the standard Buried OXide (BOX) layer is a supplementary issue in terms of thermal management (kSiO2 = 1.4W/mK when kSi = 150W/mK). Some works have already focused on alternative material for BOX replacement, by integrating CVD diamond layers, but without any proof of amelioration [1]. We have in an earlier communication already demonstrated the feasibility of the replacement of the standard BOX in an SOI substrate with a thin CVD diamond layer, thus forming Silicon-OnDiamond (SOD) substrates [2,3]. The integration scheme used implies the growth of diamond directly on the silicon that will represent the top active layer of the final SOD substrate. However, when Bias enhanced Nucleation is used, it is likely that the ion bombardment at the first initial stage of growth result in an increased localized space charge at th
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