Study of Electrochemical Deposition of Copper and Microstructure Evolution in Fine Lines
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New York State Centerfor Advanced Thin Film Technology and Department of Physics, The University at Albany - SUNY, Albany, NY 12222 2 Currentaddress:IBM MicroelectronicsDivision, Hopewell Junction, NY 12533
Abstract As computer chip technologies evolve from aluminum-based metallization schemes to their copper-based counterparts, Electrochemical Deposition (ECD) is emerging as a viable deposition technique for copper (Cu) interconnects. This paper presents the results of a first-pass study to examine the underlying mechanisms that control ECD Cu nucleation, growth kinetics, and post-deposition microstructure evolution (self-annealing), leading to the development and optimization of an ECD Cu process recipe for sub-quarter-micron device generations. The influence of bath composition, current waveform, type and texture of Cu seed layer, and device feature size (scaling effect) on the evolution of film texture, morphology, electrical properties, and fill characteristics was investigated using a manufacturing-worthy ReynoldsTech 8" wafer plating tool. Resulting films were analyzed by X-ray Diffraction (XRD), four-point resistivity probe, Focused-Ion-Beam Scanning Electron Microscopy (FIB-SEM), and Atomic Force Microscopy (AFM). These investigations identified an optimized process window for the complete fill of aggressive device structures with pure Cu with resistivity - 2.0 ;.LQ-cm and smooth surface morphology.
Introduction As integrated circuit (IC) technologies evolve through the sub-quarter micron feature size generation, the performance limiting delay in these successive generations of ICs will move from the gate delay of the active devices to the resistance-capacitance (RC) delay of the supporting interconnect system [1,2]. Thus, maximizing the performance of IC technologies at and below the 250-nm feature size generations will require further minimization of the RC delay of the interconnect system [1,2]. A copper-based interconnect system will provide a substantial resistivity reduction relative to the currently used aluminum-based interconnect system [3,4]. However, an appropriate copper-based metallization scheme must be devised to replace the aluminum-based metallization scheme. Electrochemical Deposition (ECD) has emerged as a viable means of realizing copper (Cu) interconnects [5]. When compared to Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD), ECD more readily provides the high deposition rates and the low cost of ownership desired by the semiconductor manufacturing industry [4]. This paper presents the results of a first pass study to examine the underlying mechanisms that control ECD Cu nucleation, growth kinetics, and post-deposition microstructure evolution (self-annealing) in order to develop and optimize an ECD Cu process recipe amenable to IC technologies at and below the 250-nm feature size generation.
407 Mat. Res. Soc. Symp. Proc. Vol. 564 © 1999 Materials Research Society
Experimental Section This study was conducted using an alpha-type ReynoldsTech 8-inch wafer ECD to
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