Substrate/oxide interface interaction in LaAlO 3 /Si structures
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E6.12.1
Substrate/oxide interface interaction in LaAlO3/Si structures T. Busani1 and R.A.B. Devine AFRL-VSSE, Kirtland Air Force Base, Albuquerque, NM 87117 1 also with Université Joseph Fourier, Grenoble, France ABSTRACT Amorphous lanthanum aluminate films (LaAlO3) were deposited on Si substrates at room temperature using rf sputtering in pure Ar or an Ar/O2 mixture with a stoichiometric target. The film composition was analyzed using XPS and EDX. The evolution of the material resulting from annealing at temperatures in excess of 900 °C was studied using infrared spectroscopy, XPS profiling and AFM. We obtain clear evidence for in-diffusion of Si from the substrate into the dielectric film. FTIR analysis showed only one peak centered at 747 cm-1 with an FWHM of 185 cm-1 for as-deposited samples indicating an amorphous structure. Annealed samples showed very narrow absorptions at 483-510, 607, 695-720 and 811 cm-1. No evidence for SiO2 peaks at ~1060 cm-1 was observed suggesting that the LaAlO3 structure tends not to reduce into a mixture of SiO2 and a silicide. Short time annealing at 1000 °C results in a broad band at 905 cm-1 which can be interpreted in terms of the formation of a layer rich in Si-O-La bonds. Nitridation of the substrate before oxide deposition and annealing slows the degradation process but does not suppress it. X-ray diffraction analysis of the annealed films indicates a very oriented crystalline structure, yet unidentified, whose direction depends upon the orientation of the Si substrate. The dielectric constant in both annealed and as-deposited films was measured to be less than 14 and the leakage current density was very low. Some mobile charge was detected. This dielectric constant is substantially less than the value ~ 25 anticipated from bulk, single crystal measurements. INTRODUCTION The dramatic expansion in technology and the communications market, including the one associated with high performance microprocessors as well as low-static power applications such as wireless systems [1], has driven industry to require greater integrated circuit functionality and performance at lower costs. This means an increase in circuit density for each Si wafer [2]. Obviously, device channel length and the SiO2 gate dielectric thickness must decrease. However, SiO2 layers thinner than ~ 1.3 nm have excessive leakage current (> 1 A/cm2) simply due to direct tunneling through the oxide, and this is far too large for future circuits [3]. Unfortunately, the Semiconductor Industry Association road map indicates that a sub-1 nm effective oxide thickness (EOT) will be required for complementary metal-oxide-semiconductor (CMOS) devices with 50 nm gate widths so a dilemma exists. An acknowledged solution (in principal) to the leakage current issue is to maintain the gate capacitance by increasing the dielectric constant (k) of the oxide and simultaneously thicken it. Though it is unlikely that the alternative oxide will have the excellent leakage properties of thermally grown SiO2, a compromise may exist. Many
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