Temperature Dependent Carrier Transport in Single-Crystalline Si TFTs inside a Location-Controlled Grain
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Temperature Dependent Carrier Transport in Single-Crystalline Si TFTs inside a Location-Controlled Grain V. Rana1, R. Ishihara1, Y. Hiroshima2, D.Abe2, S. Inoue2, T. Shimoda2 , J.W.Metselaar1 and C. I.M Beenakker1 1 Delft Institute of Microelectronics and Submicrontechnology (DIMES), Delft Univ. of Technol., Delft The Netherlands 2 Technology Platform Research Center, Seiko-Epson Corp., Nagano, Japan ABSTRACT Temperature dependant I-V characteristics were measured on single-crystalline Si (c-Si) TFTs fabricated inside a location-controlled grain by µ-Czochralski process using an excimer-laser. At ON-state, temperature the activation energy (Ea) of the drain current drops to a negative value. The field effect mobility (µFE) also decreases with temperature with a power of -1.86, which indicates that, the carriers transport are governed by acoustic phonon scattering. At OFF state with a small gate bias, leakage current is dominated by thermal generation, however the Ea was 0.9eV, i.e., near the band gap value of Si. This suggests that the carrier generation centers are not located at the mid-gap states. These distinctive results from a typical poly-Si TFTs are systematically investigated for c-Si TFTs having ECRPECVD and LPCVD SiO2 gate insulator. INTRODUCTION Excimer-laser crystallization of a-Si film [1] provides a powerful tool for realizing formation of poly-Si TFT at a low temperature for active-matrix liquid crystal displays (AMLCDs). There reported many ways of lateral solidification (1D location control of grain) and TFT fabricated parallel to grain boundaries (GBs) for improvement the TFT characteristics [2]. On the other hand, precise location-control of a grain in excimer-laser crystallization process allows us to completely eliminate the GBs from active area of thin film transistor, i.e. single-crystalline Si TFTs (c-Si TFTs). TFTs fabricated inside a locationcontrolled grain by µ-Czochralski process [3] showed a high field-effect mobility of 600 cm2/V.s and small subthreshold slope (S) value of 0.2 V/dec. [4]. The high performance of the c-Si TFTs will allow us to integrate system circuits as well as driver circuits with display, i.e., system on glass. In conventional poly-Si TFTs, the ON current is governed by the potential barrier formed at high angle GBs, even at a high gate bias [5]. The leakage current arises from the generation of carriers in the depletion layer formed between the drain and channel. The mechanism of leakage current is recognized either as pure thermal generation or field enhanced carrier emission from traps, with a moderate or strong drain bias conditions, respectively. In present work, to investigate the mechanism of carrier transport of the c-Si TFTs in detail, temperature dependence of I-V characteristics were studied, of the c-Si TFTs with ECR-PECVD or LPCVD SiO2 gate insulator fabricated inside a location-controlled grain by µ-Czochralski (grain-filter) process. EXPERIMENT The n-channel, single-crystalline Si TFTs used in this study was the same as the one reporte
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