Monolithic 3D Integration of Single-Grain Si TFTs
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1066-A20-06
Monolithic 3D Integration of Single-Grain Si TFTs Mohammad Reza Tajari Mofrad, Ryoichi Ishihara, Jaber Derakhshandeh, Alessandro Baiano, Johan van der Cingel, and Cees Beenakker Department of Electrical Engineering, DIMES/ECTM, Technical University of Delft, Delft, Netherlands ABSTRACT Vertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. NMOS mobilities are 565 and 393 cm2/Vs and pMOS mobilities are 159 and 141 cm2/Vs, for the top and bottom layers respectively. A three-dimensional (3D) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer. The inverters showed an output voltage swing of 0 to 5 V with a switching voltage of around 2 V. INTRODUCTION Down-scaling of transistors increases the density of the chip and the interconnects. Higher device density needs more space reserved for routing purposes, which decreases the advantage of down-scaling. Also the interconnect delay increases in such a way that becomes the limiting factor for circuit performance [1]. Three-dimensional integration is a solution for these issues as it decreases the interconnect length and power consumption. It also increases the functionality of a chip by enabling integration of a sensor layer on top of it. High-density ICs may be manufactured using the existing industrial infrastructure, eliminating the expenses required for developing new equipment or new sub-micron processes. 3D integration may be in package level, wafer level [2][3] or device level. The first two suffer from the low interconnect density between the stacked layers limited by the alignment accuracy of about 1 µm, between the packages or the wafers. Vertical stacking in device level, or monolithic integration, results in the largest decrease in interconnect length decrease, highest density of interconnects between the successive active silicon layers and offers new routing possibilities crucial to system-on-chip (SoC) design. Device level integration of electronics started in the early eighties. The first attempts towards monolithic fabrication were not successful [4][5]. Regardless of the approach, the main issue was the high temperature (>600 °C) needed to form high quality silicon for the top layers, which caused doping redistribution in the bottom layers [6]. Another limitation was the usage of single-crystalline Si wafer as seeding the top layer Si growth in other successful results[7]. This limits the application to microelectronics only and is useless for large area electronics.
The SG TFT are aimed at obtaining characteristics comparable to CMOS devices by placing the channel of a TFT inside a single grain. Single-grain location-controlled silicon is obtained by the so-called µ-Czochrolski process which is a location-controlled crystallization method
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