The Application of Solid Source Diffusion in the Vertical Replacement-Gate (VRG) MOSFET
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The Application of Solid Source Diffusion in the Vertical Replacement-Gate (VRG) MOSFET Sang-Hyun Oh, J.M. Hergenrother, Don Monroe, T. Nigam, F.P. Klemens, A. Kornblit, W.M. Mansfield, F.H. Baumann, H.J. Gossmann, C.A. King, R.N. Kleiman, H-H. Vuong, G.R. Weber, and C.S. Rafferty Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA Abstract We discuss the first use of solid source diffusion (SSD) to form shallow, self-aligned SDEs in a novel device known as the Vertical Replacement-Gate (VRG) MOSFET. This is the only MOSFET ever built that combines 1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and 2) a high-quality gate oxide grown on a single-crystal Si channel. The use of SSD in this novel geometry allows us to transform the precise gate length control afforded by the VRG process into precise, lithography-independent channel length control. In the VRG-nMOS process, silicon nitride offset spacers separate the phosphosilicate glass (PSG) SSD dopant sources from the polysilicon gate. These offset spacers, whose critical dimensions are also controlled by film thicknesses, allow us to precisely tune the gate-source and gate-drain overlaps in order to optimize the capacitance/series resistance tradeoff. These parasitic overlap capacitances have precluded the high-frequency operation of many previous vertical MOSFETs. In this paper, we discuss the SIMS and sheet resistance characterization of shallow phosphorus junctions formed in one-dimensional SSD experiments. We will also discuss the scanning capacitance characterization of two-dimensional doping profiles of VRG-nMOSFETs with gate lengths down to 50 nm. Introduction We have demonstrated a new device called the Vertical Replacement-Gate (VRG) MOSFET [1, 2]. This is the first MOSFET ever built in which 1) all critical transistor dimensions are controlled precisely without lithography, 2) the gate length is defined by a deposited film thickness, independently of lithography and etch, and 3) a high-quality gate oxide is grown on a single-crystal Si channel. Although many approaches have been used to build vertical MOSFETs on the sidewalls of trenches or Si pillars [3-10], all previous vertical MOSFETs have lacked at least one of the following essential characteristics of the advanced planar transistor: high-quality gate oxide, sufficient gate length control, self-aligned S/D, and low parasitic capacitances. We have used solid source diffusion (SSD) to form self-aligned, shallow SDEs in the VRGMOSFET and have demonstrated a 50-nm MOSFET that is built using production tools. The VRG-MOSFET Process The key enabling element of the VRG process is its replacement-gate approach - this allows for the fabrication of high-quality gate oxides on a vertical {100} Si surface whose length is defined by a film thickness. The VRG process is outlined in Fig. 1.
B3.2.1
Epi
Implant Drain
Deposit Stack
Etch Trench
Grow Channel
CMP
Dep. Source Pad Source Gate
Gate Drain
Pattern Pad
Deposit Nitride S
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