The Detrimental Effect of a Passivation on the Electromigration Lifetime of Narrow Al-Si-Cu Lines

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ABSTRACT 2 mm long, 0.8 gtm wide and 0.8 gim thick Al-Si-Cu lines, passivated with a 1.14 gim thick PETEOS SiO 2 were found to have a lower electromigration lifetime compared to identical unpassivated lines. The high tensile stress in the passivated lines is assumed to accelerate electromigration failure. This is confirmed by the very low activation energy for electromigration failure in the passivated lines and by the multiple events of recovery during and after electromigration testing, suggesting failure sites are slit voids.

INTRODUCTION In the literature many experiments [1-3] have shown the beneficial effects of a passivation on the electromigration lifetime. One of the explanations for this increase in electromigration lifetime has been the difficulty to form electromigration hillocks in a passivated material. However, recently it has become clear that a passivation also can have a detrimental effect on the reliability. Passivated Al-based interconnects are susceptible to stress migration [4]; t.i. the formation of voids due to the migration of Al atoms under the driving force of a high tensile stress. This tensile stress develops in the Al-lines after cool down from a high temperature treatment (e.g. passivation) and is caused by the difference in thermal expansion between the Al and the Si-substrate on one hand and the passivation material on the other hand. It also has been shown, both theoretically [5] and experimentally [6] that these thermal stress induced voids can decrease the electromigration lifetime. But even without pre-existing voids, it was shown theoretically that a tensile stress can accelerate electromigration failure significantly [7]. In this work we present experimental evidence which is in agreement with this idea.

SAMPLE PREPARATION 800 nm thick Al-Si-Cu layers were sputter deposited from an Al-1 wt. % Si-0.5 wt. % Cu target in a CLC9000/GalaxylOO cluster tool on 5" thermally oxidized Si (100)-wafers. A three step deposition process (to minimize the amount of etch residues and optimize the step coverage) at a chuck temperature of 300 *C was used. The 2 mm long, 0.8 mim wide, 4-point contacted, straight line electromigration structures with a bonding pad layout as defined by the NIST standard [8] were defined by standard i-line lithography and reactive ion etching. Part of the structures were passivated, the others were kept unpassivated. The passivation is a 1.143 ± 0.003 jim thick SiC 2 layer, deposited at 390 'C by Plasma Enhanced Chemical Vapor Deposition from a Si(OC 2 H 5 )4 precursor (= PETEOS) in a single wafer system (Applied Materials P-5000 PECVD) with a deposition rate of 800 nm/min. Cool down both after metal deposition and passivation deposition was fast as wafers were transported by a robot arm to a cooling chamber after metal deposition and to a metal cassette after passivation. After this wafers were diced and 447

Mat. Res. Soc. Symp. Proc. Vol. 391 01995 Materials Research Society

electromigration samples were bonded in pairs to 40-pin ceramic packages using a poly

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