The Path Towards Woven Thin-film Transistors
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The Path Towards Woven Thin-film Transistors Kunigunde Cherenack, and Gerhard Tröster Gloriastrasse 35, Zürich, 8092, Swiss Federal Institute of Technology
ABSTRACT Electronic textiles (or e-textiles) have a wide range of potential applications in wearable computing and large-area applications, including medical monitoring, assistance to the disabled, and distributed sensor networks. We aim to integrate thin-film electronics directly into clothing during the weaving process. First, thin-film devices are fabricated on plastic substrates. Individual devices are separated by cutting the substrate into stripes which can then be woven into a textile. Devices on stripes need to survive high applied bending strains during weaving. As a first building block, we used atomic layer deposition (ALD) at a maximum temperature of 150oC to fabricate bottom-gate zinc-oxide thin-film transistors (TFTs) with a 25nm-thick Al2O3 gate dielectric, and a 15nm-thick ZnO semiconducting layer on 50μm-thick Kapton E substrates. These TFTs had average mobilities of 12cm2/Vs, threshold voltages around 1V and subthreshold slopes around 250mV/decade. However, after applying a tensile bending diameter of 1cm to the TFTs, ~80% of TFTs fail due to cracking of the brittle device layers. We studied causes of failure and investigated patterning holes in the brittle layers to prevent crack propagation though the channel. This reduced TFT failure to ~45% under the same applied bending conditions. In this paper, we will discuss failure mechanisms in our standard TFT structure when high tensile bending strains are applied and how the device structure was adjusted to decrease TFT failure.
INTRODUCTION Flexible electronics represent the next evolutionary development within the field of microelectronics and enable a wide range of novel applications including paper-like displays [1], smart textiles [2] and large-area sensor arrays [3]. In comparison to devices fabricated on rigid silicon or glass substrates, devices on flexible substrates may experience high mechanical strain, resulting in circuit failure due to device layer cracking. Finite element studies have shown that ductile copper metal films which are well bonded to Kapton polyimide substrates can be stretched well beyond their bulk rupture strain due to strain delocalization of the substrate [4] and researchers have measured tensile rupture strains for thin-film copper metal on Kapton substrates up to 50% and higher [5]. However, brittle device layers will fail at around 2% strain [6]. Therefore it is critical that the strain in brittle device layers is reduced below the value at which cracking is initiated. Methods of reducing the strain experienced by device layers include preventing the propagation of cracks through the device layers though nano-patterning [7], reducing the strain in layers below the fracture limit of the material by patterning islands [8] or shifting the critical device layers closer to the neutral bending plane [9,10]. In this paper we investigate the cracking behav
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