The Two-Step Growth Mechanism of MOCVD GaAs/Si
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THE TWO-STEP GROWTH MECHANISM OF MOCVD GaAs/Si
KOICHI ISHIDA* Optoelectronics Joint Research Laboratory 1333 Kamnikodanaka, Nakahara-ku, Kawasaki 211, Japan
Abstract The growth mechanism and lattice defects are studied for GaAs/Si grown by the two-step MOCVD growth procedure using transmission electron microscopy (TEM). The large misfit stress between GaAs and Si is relieved by misfit dislocations at the GaAs/Si interface, which are introduced during epitaxial
regrowth of the thin ( 10 6 cm-2 ) of the threading dislocations in the GaAs layer, contrary to the results of molten KOH etching.
Introduction In recent years, epitaxial growth of GaAs on Si has gained increasing interest, since such a system presents possibilities for novel integrated devices based on GaAs and Si [1]. However, the large lattice misfit between GaAs and Si (-4%) and the growth of polar crystal on non-polar one cause generation of lattice defects and antiphase disorder. To overcome these problems, the use of several kinds of hetero-buffer layers has been tried [2, 3]. It has been shown recently that a good quality GaAs layer free from antiphase domains can directly be grown on Si by MOCVD [4] and MBE [5, 6] two-step growth. However, the growth mechanism of the two-step growth was not clear. In this paper, we study the lattice defect structures in GaAs/Si grown by the MOCVD two-step growth by transmission electron microscopy (TEM) and clarify the growth mechanism. The results are compared with those observed for GaAs/Si grown by MBE [7, 8].
Experiment The GaAs layer was grown by the MOCVD two-step growth on (001) Si substrates [4]. The Si substrate is a commercially available (001) wafer oriented within 0.50. After cleaning the substrate surface by heating above 900°C, a thin buffer layer (100-200A thick) was first grown at low temperature (400-4500 C), *Present address: NEC Fundamental Research Laboratories 4-1-1, Miyazaki, Miyamae-ku, Kawasaki, Kanagawa 213, Japan
Mat. Res. Soc:: Syruip. Proc. Vol. 91
1987 Materials Research So~ciety
134
and subsequently, a thick GaAs layer was grown at normal growth temperature (-7500 C). For comparison, some epitaxial layers were grown at 750°C without the buffer layer. The lattice defects at the GaAs/Si interface and in the GaAs layer were studied by TEM with JEOL 200CX. To investigate the specific positions of GaAs layers, different kinds of TEM specimen were prepared. To study the interface structure, we used thin (-500A) epitaxial layers; the TEM specimens prepared by backside thinning the Si substrate always contain the GaAs/Si interface. The threading dislocations in the GaAs layer were examined by using thick (1-3 pm) epitaxial layers. By preparing the TEM specimen of the surface regions and various depths of the GaAs layers, one can study the configuration of threading dislocations. The molten KOH etching was performed at 360°C for one-two minutes. To compare the results obtained by TEM observations with those by molten KOH etching, TEM specimens were prepared after molten KOH etching of t
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