From planar to vertical nanowires field-effect transistors
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From planar to vertical nanowires field-effect transistors Guillaume Rosaz1, 2, Bassem Salem1, Nicolas Pauc2, Pascal Gentile2, Priyanka Periwal1, Alexis Potié1, Thierry Baron1, L. Latu-Romain1, S. David1 1 Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France 2 CEA, INAC/SP2M, Laboratoire SiNaPS, F-38054 Grenoble, France ABSTRACT The authors present the technological routes used to build planar and vertical gate allaround (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104 but with poor dynamics which can be explained by the high interface traps density. INTRODUCTION NWs have attracted a lot of attention during past years because of their promising applications1,2,3,4. It has been demonstrated that these nanostructures can be used as a conduction channel in FETs5, 6, 7. The growth of these NWs by bottom up approach using Vapor-liquid-Solid (VLS) mechanism is very interesting because of the possibility to obtain crystalline materials at low temperature. Due to this reason, it can be applied to back end steps in Integrated Circuits (IC’s). The introduction of Ge in the gas phase allows reducing the growth temperature from 650 °C for Si NWs to 400 °C for SiGe NWs as shown by Potié et al8. Therefore, Ge addition does not only reduces the growth temperature but due to higher mobilities of their carriers, they are favored and suitable for high speed electronics. Due to the challenge involved in the positioning of single NWs many research teams have shown the possibility to organize these structures on surfaces using complex approaches9. Recently vertical devices have been shown 10, 11, 12, 13 and these devices offered easier positioning by means of lithography and also the possibility to easily build a wrapping gate, which enhances the electrostatic control of the channel. We show in this paper the technological steps involved for the realization of both planar and vertical devices and present their electrical characteristics. EXPERIMENT Si and SiGe NWs were grown using a Chemical Vapor Deposition (CVD) tool by the VLS mechanism. Gold colloids of diameter 100 nm were used as catalyst. Firstly, we will present the growth and elaboration of planar FETs devices and secondly the realization of vertical NWs FET. More detailed procedures can be obtained in our previous publications 14, 15, 16
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Planar FETs fabrication Gold colloids were
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