Thin Film Power Harvesting System for Displays
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Thin Film Power Harvesting System for Displays Arman Ahnood1, Reza Chaji2, Arokia Nathan1 1. London Center for Nanotechnology, University College London, UK 2. IGNIS Innovation Inc., Kitchener, Ontario, Canada ABSTRACT An amorphous silicon (a-Si:H) thin film transistor (TFT) circuit designed for charging of an energy storage device using a photovoltaic (PV) array is presented. The TFT circuit is fabricated at plastic compatible temperatures (~150°C) and as such can easily be integrated within a range of platforms including flexible displays. The circuit provides a high degree of output voltage stability over a range of light intensities and device stress. INTRODUCTION Consumer requirements for handheld mobile devices include longer battery life, so that mains recharging can be performed less frequently. To this end a key component of any mobile system is a high power and high energy density battery. An alternative approach to extend battery lifetime for handheld devices is to recycle some of their own energy consumption or harvest energy from ambient sources. Displays are one of the most power consuming components of mobile devices. In modern mobile devices, the display occupies a substantial portion of the exposed area. By designing a display such that it also functions as a “solar cell” it is possible to harvest some of the ambient light energy [1-3]. Given the scope for power harvesting, it is important to investigate their implementation and integration. In this work we present a TFT based circuit capable of regulating the output power of a PV array for storage in a battery or supercapacitor. The schematic shown in Figure 1 indicates how the TFT charging circuit fits within the system. The power conditioning circuit considered here fulfils two roles: a) Limits the charging voltage to avoid damage to the energy storage device. Furthermore, a narrower voltage range at the energy storage device will allow for a more efficient design of the power circuitry in mobile devices. b) Provides input impedance to the PV array such that it would operate close to its maximum power point. EXPERIMENTAL Figure 2 shows the cross sectional diagram of the TFT used in the circuit. The TFTs were fabricated using the etch stop (ES) process[4]. The device structure consists of 50nm amorphous silicon (a-Si:H) channel layer, 300nm silicon nitride (SiNx) gate dielectric layer, and 50nm n-type nano-crystalline silicon Figure 1. Overview of onpanel power harvesting (nc-Si:H) contact layers. All of the films were deposited using system for displays. radio-frequency plasma enhanced chemical vapour deposition (RF-PECVD) at the 150°C in a two chamber system. The aSi:H was deposited in a dedicated intrinsic chamber using SiH4/H2/He with gas flow rates of [2]/[15]/[5] sccm at 0.8 Torr pressure and 21mW/cm2 RF power density. The SiNx was 413
deposited at a pressure of 1Torr using a mixture of SiH4/H2/NH3 with gas flow ratios of [4]/[40]/[120] sccm at 125mW/cm2, 200Hz pulsed-RF (50% duty cycle) power. The deposition of n-type nc-Si:H was performe
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