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ABSTRACT This study reports on the fabrication of inverted gate TFT devices and circuits using a low temperature microcrystalline silicon deposition process compatible with polyimide substrates. Results from the electrical and material characterization of tt-Si:H based TFT's are presented. Device performance is compared with that of a-Si:H based TFT's constructed on polyimide. Results indicate that the anticipated improvement in device performance due to an increase in the p-Si:H Hall mobility (-10 cmVV-sec) over that of a-Si:H (-I cmVV-sec) is not realized. Properties of pt-Si:H films are related to deposition parameters. INTRODUCTION Microelectronic devices based on thin film transistors (TFT's) are currently being manufactured on glass substrates for various LCD display technologies. Polycrystalline silicon is typically used as the active layer to achieve switching speeds and drain currents approaching those of crystalline silicon. However, efforts to build similar devices on flexible polymeric substrates have been hampered by the limits placed on processing temperatures by the polymers (< 350'C). Devices fabricated on polyimides therefore currently employ amorphous silicon (a-Si:H) which can be deposited at suitably low temperatures [1-3]. These aSi:H based devices exhibit lower performance than their polycrystalline counterparts, due in part to the significantly lower mobility of a-Si:H (-1 cm 2/V-sec ) compared with that of poly-Si (- 100 cm/V-sec). Switching speeds for these devices are on the order of 1 msec with typical IDS= 10 0 p-A (at VDS=IOV, Vos=IOV) for devices with L=2 pm and W/L =10. This study reports on the fabrication of inverted gate TFT devices using a low temperature microcrystalline silicon (pt-Si:H, -10 cm/V-sec) deposition process compatible with polyimide substrates. EXPERIMENT The devices and circuits fabricated in this study employ an inverted gate TFT structure. A cross-sectional diagram is given in Figure 1. The entire process requires 7 photolithographic masking steps. For devices constructed on polyimide, a conformal coating of 6 ptm thick polyimide is applied onto the 4-inch wafer using the spin-on technique. The wafer provides rigid backing for lithography alignment. The film is then cured in several stages up to 350'C. The polyimide is next passivated by depositing 1000 A of PECVD oxide (SixOy:H) using Sill4 and N2 0 at 2750 C. The first step in TFT fabrication is the deposition, patterning and etching of a 500-1000 A thick chromium layer to create the inverted gate electrode. The gate dielectric is deposited in a two step process. A 1000 A layer of PECVD oxide is deposited first followed by a 300-500 A layer of PECVD oxy-nitride (SixOyNliy:H), both at 2750 C. The oxy-nitride layer is added because it has been shown to yield a lower surface defect density at the a-Si:H/gate dielectric 683 Mat. Res. Soc. Symp. Proc. Vol. 557 ©1999 Materials Research Society

PECVD Oxide Dielectric Passivation

Cr tordn Cap PECVDSi:

5

(c or t.) n+ contacts

PECVD

Oxy-Nitride Dielectric PECVD Ox