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Namely, the TFTs exhibit a threshold-voltage shift after prolonged application of gate voltage. For moderate voltages this is ascribed to the creation of dangling-bond defects in the a-Si:H within the channel region. For higher voltages also charge trapping in the gate dielectric is expected [1-3]. Both effects imply a variation of the space-charge layer in the channel, thus resulting in a shift of the TFT on-set voltage. The effect can be reversed by annealing at high temperatures. In order to investigate this metastability of a-Si:H several groups have extensively studied a-Si:H TFTs over the last two decades ([4-6] and references therein). By applying gatevoltage stress, the Fermi level in a-Si:H can be controlled and shifted without the influence of any doping atoms. The equilibrium defect distribution in a TFT changes due to this Fermi level shift, as described by the defect-pool model [7]. So far, only a few groups reported on hot-wire CVD (HWCVD) material included as active layer in a-Si:H TFTs [8-10]. We found for such HW-TFTs incorporating a-Si:H or heterogeneous-Si:H i-layers an essentially higher stability compared to their PECVD counterparts [11,12]. Also, deposition rates higher than 1.5 nm/s were readily obtained, which makes this deposition technique promising for industrial application. In this paper we report on TFTs including I-HW a-Si:H i-layers deposited on PECVD silicon-nitride and thermally grown silicon dioxide (SiO 2). By comparing the two types of TFTs with different insulators, the influence of the dielectric material on the device performance is studied.

659 Mat. Res. Soc. Sytnp. Proc. Vol. 557 ©1999 Materials Research Society

EXPERIMENTAL

TFT preparation We studied three kinds of TFTs of the inverted-staggered type including different types of a-Si:H layers. The device structure is sketched in Fig. 1. Two samples (A, B) have an intrinsic a-Si:H layer deposited by HWCVD. For sample A the aSi:H layer is deposited on 300 nm silicon nitride (aSiN,:H), for sample B it is deposited on 160 nm SiO 2. As reference we used a TFT with a layer of

2,

.is U•puaILwAU% Y , nitride (C). The deposition of the NM,-Iz on silicona-o U`vLw%quaaLty

devices

was

performed

in

two

multi-chamber

5Onm n+

|

00nm a-SI:H a5S0H 5200nm

160nm Si0, or 300nm SINx

p type c-Si substrate Fig.1 Cross section ofaTFT. The highly doped substrate is the gate (not to scale).

ultrahigh-vacuum CVD systems. We used our system ASTER [13] for all silicon nitride depositions and a-Si:H deposition for sample C. The HW i-layers and glow-discharge n+-contacts for samples A and B were deposited in our system PASTA [14]. In contrast to samples A and B, sample C was completely deposited within one system without exposure of the dielectric to air. As substrate we used highly doped p-type c-Si wafers (0.010 - 0.018 Q)cm), which form also the gate contacts. In order to remove the native oxide before a silicon-nitride deposition, the wafer was dipped in 0.5 % hydrofluoric acid before loading into the deposition system. The aSiN,:H