Three-dimensional integration: An industry perspective
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Introduction A combination of lithographic scaling, device scaling,* and the introduction of innovative materials has produced an incredibly sustained gain in silicon productivity as measured by the cost per transistor and power-performance per transistor, and thus, cost per function. This is often popularly interpreted as Moore’s Law. More recently, indications show this trend is slowing down. For example, as pointed out by Or-Bach,1 so-called 14 nm static random access memory cell sizes are approximately 60% larger than what would be predicted by straightforward scaling—although the move to vertically oriented fin-shaped field-effect transistors has provided a significant one-time bump in many of these metrics. It is important to point out that it is not physics, materials, or even technology that is preventing further scaling but rather the effective manufacturing cost per transistor. This is driven primarily by an ever-increasing bill for manufacturing equipment, complexity (especially in lithography and patterning), and the amortization of the cost of development. Non-recurring engineering is another component of cost that includes chip design under restrictive rules, change orders, and mask costs, which are also increasing at unsustainable rates.
However, there are other aspects of system scaling that can come into play. We turn our attention to the package and the board. Interestingly, referring to Figure 1, while silicon has scaled by about a factor of 1000 since the 1970s, almost every key parameter in the package and the board has scaled by a mere factor of three to four during the same time frame. There are sound reasons for this neglect in scaling packaging features. Silicon scaling was delivering on cost, performance, and density in a very predictable manner (see the Introductory article in this issue). As a result, more circuitry could be assembled on a single die, leading to the system-on-a-chip (SoC) era. This allowed for more functional integration; consequently, different functional blocks communicated on the same die without needing to go off-chip. This meant there was more return on investment to scale silicon versus improving the package and board level interconnects, allowing systems to operate with the lowest latency and highest bandwidth.† However, this on-chip interconnection comes at a cost: The die sizes were getting larger and the processes were getting more complex, both of which result in reduced yield.
†
Latency refers to the time it takes for data to reach its destination after being
*A recent retrospective of Dennard’s scaling theory by M. Bohr is available at
requested, a measure of delay that includes logic operations and transit time, while
http://www.eng.auburn.edu/∼agrawvd/COURSE/READING/LOWP/Boh07.pdf and also
bandwidth refers to how much data may be transferred in a unit of time—a measure
in the January 2007 issue of the IEEE Journal of Solid-State Circuits Society.
of how many interconnects exist between two system nodes.
Subramanian S. Iyer, Microelectronics Division
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