Time-Interleaved SAR and Slope Converters
This paper investigates time-interleaved SAR and time-interleaved slope converters, targeting low-power, low-resolution, high-speed applications. Fundamentally, these two architectures can be relatively power-efficient as compared to other architectures.
- PDF / 1,054,628 Bytes
- 19 Pages / 439.37 x 666.142 pts Page_size
- 88 Downloads / 174 Views
Time-Interleaved SAR and Slope Converters Pieter Harpe, Ming Ding, Ben Bu¨sze, Cui Zhou, Kathleen Philips, and Harmke de Groot
Abstract This paper investigates time-interleaved SAR and time-interleaved slope converters, targeting low-power, low-resolution, high-speed applications. Fundamentally, these two architectures can be relatively power-efficient as compared to other architectures. At the same time, complex calibration schemes are not required thanks to their inherent accuracy. The architectures are examined and compared, circuit implementations and measurement results are discussed and an outlook to the future will be given.
3.1
Introduction
Wireless communication standards using Impulse Radio UWB (IR-UWB), like 802.15.4a WPAN and 802.15.6 WBAN, require low-power, low-resolution (3–6 bit), high-speed (0.5–2 GHz) AD converters [1, 2]. Because of the high speed of operation, flash-based converters are often selected for this application [3], but alternatives based on pipelining [4] or SAR [5] are also being developed. When deciding for a suitable ADC architecture, one could either take the high-speed requirement or the low-power aim as a starting point. Both these approaches will be briefly discussed in the following sections.Eventually, the time-interleaved SAR and slope architectures are chosen for further analysis and implementation.
P. Harpe (*) Holst Centre and imec, Eindhoven, The Netherlands Eindhoven University of Technology, Eindhoven, The Netherlands e-mail: [email protected] M. Ding • B. Bu¨sze • C. Zhou • K. Philips • H. de Groot Holst Centre and imec, Eindhoven, The Netherlands A.H.M. van Roermund et al. (eds.), Nyquist AD Converters, Sensor Interfaces, and Robustness: Advances in Analog Circuit Design, 2012, DOI 10.1007/978-1-4614-4587-6_3, # Springer Science+Business Media New York 2013
31
32
3.1.1
P. Harpe et al.
High-Speed Approach
When focussing on speed, flash and pipelined architectures offer an advantage because of the parallel operation of hardware: flash converters use a set of parallel comparators to maximize speed, while pipelined ADCs can decide the various bits in parallel by pipelining the operations. While this is advantageous for speed, it also leads to drawbacks in terms of power-efficiency and calibration complexity. In case of an N-bit flash converter, the number of comparators equals 2N 1. Noting that the power consumption of the comparator is an important contributor to the overall power, the exponentially increasing number of comparators implies that the power-efficiency may be sub-optimal as compared to e.g. an architecture in which the number of comparators grows linear with the resolution N. To improve the power-efficiency of flash converters, the devices in the comparators are usually reduced in size to minimize the power consumption. In this way, excellent powerefficiencies are feasible such as demonstrated in [3]. However, the drawback of these down-scaled devices is the increase of mismatch, which limits the intrinsic linearity that can be achieved. Thi
Data Loading...
