Titanium Silicides and Their Technological Applications
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L.A. Clevenger and R.W. Mann' IBM T.J. Watson Research Center, Yorktown Heights, NY 10598 'IBM Microelectronics, Essex Junction, VT 05452
Abstract Titanium silicides are used as source, gate and drain contacts and local interconnections in CMOS integrated circuits. In these applications, it is important that the titanium silicide phase have a low resistivity (< 20gQ-cm) and not agglomerate during high temperature processing. The Ti/Si system has two silicide phases that are useful for electronic applications, high resistivity C49-TiSi 2 (60-70 4gQ-cm) which forms at 600 - 700'C and low resistivity (15-20 AuQ-cm) C54-TiSi 2 which forms from 700 to 850'C. This paper will review how the size of the thermal annealing process window for forming low resistivity C54-TiSi 2 from high resistivity C49-TiSi 2 without having the silicide agglomerate varies with annealing treatments, electronic dopants, and contact size. In addition, processing methods to improve the size of the process window will be discussed. Introduction Thin film silicide phases have generated interest in the semiconductor industry over the last 15 years due to their applications in very large scale integration (VLSI) and ultralarge scale integration (ULSI) CMOS integrated circuits.1' 2 This is due to the fact that the use of silicides allows for the formation of low resistance source, gate and drain contacts which can significantly reduce the resistance of a CMOS gate conductor and/or the source/drain series resistance compared to non-silicided structures.3 5 The lower resistance of silicide CMOS contacts gives improved device performance in terms of switching speed or source/drain drive current. Figure 1 shows the impact of CMOS gate conductor sheet resistance on the performance of a 51-stage CMOS ring oscillator with 0.7 im effective gate length. 6 Without any silicide present, the delay time at 5V is about 300 ps while with increasing initial Ti thicknesses used to form thicker titanium silicide contacts with increasing lower sheet resistances, the signal delay time at 5V can be reduced to 46 ps. In this paper, an overview of titanium silicide applications in integrated circuits is presented focusing on processes to obtain low resistance, thermally stable titanium silicide source, gate and drain CMOS contacts. The emphasis is on the parameters which degrade thermal process windows for both the formation of the low resistance C54-TiSi 2 phase and its subsequent higher temperature agglomeration, and on how to use extrinsic processing methods to enlarge thermal process windows. 15 Mat. Res. Soc. Symp. Proc. Vol. 320. -1994 Materials Research Society
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Figure 1: Measured delay time/stage of a 51-stage ring oscillator with 0.7 tm gate length as a function of initial Ti thickness reference 6).
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Results and Discussion Two main types of silicide processes are used in the semiconductor industry: Salicide and Polycide. A schemati
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