Transmission Electron Microscopy Studies of Strained Si CMOS
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Transmission Electron Microscopy Studies of Strained Si CMOS Qianghua Xie, Peter Fejes, Mike Kottke, Xiangdong Wang, Mike Canonico, David Theodore, Ted White1, Mariam Sadaka1, Victor Vartanian1, Aaron Thean1, Bich-Yen Nguyen1, Alex Barr2, Shawn Thomas3, Ran Liu4 Advanced Products Research and Development Laboratory, Freescale Semiconductor Inc., Tempe AZ 85248 1 Advanced Products Research and Development Laboratory, Freescale Semiconductor Inc., TX 78721 2 Crolles-2, Freescale Semiconductor, 870 rue Jean Monnet 38926 Crolles, France 3 Embedded Systems and Science Research Laboratory, Motorola Inc., Tempe AZ 85248 4 School of Micro-electronics, Fudan University, Shanghai 200433, China ABSTRACT In this paper, various types of defects (both threading dislocation and misfit dislocations) in strained Si (sSi) have been analyzed by transmission electron microscopy (TEM). Germanium upper-diffusion has been studied by scanning transmission electron microscopy (STEM) for strained Si on SiGe/SOI. SGOI-devices processed using an optimized thermal budget show minimal Ge diffusion and minimal process related defects. Correlation between the device performance (such as leakage current and reliability) and structural information found in TEM has been established. INTRODUCTION There has been extensive development and research work done to introduce strained Si (sSi) to CMOS platforms taking advantage of its enhanced carrier mobility [1]. One of the earlier approaches uses biaxially strained Si on a composition graded relaxed SiGe buffer [2]. The later ones include the introduction of tensile or compressive stressors [3]. Various substrates for sSi have been developed such as strained Si on SiGe/insulator (SGOI) [4] or strained Si on insulator (SSOI) [5]. The strain in sSi makes the structure meta-stable and imposes several challenges for material fabrication (such as defect formation and surface roughness). Furthermore, the compatibility of sSi with CMOS processes needs to be examined. For instance, Ge diffusion may cause degradation of strain in sSi channels and may act as traps in the gate dielectric causing potential device instability [6, 7]. This concern may become more prominent when reducing the sSi channel thickness to minimize defects. Misfit dislocations at the sSi-SiGe heterointerface arising from sSi relaxation could also pose serious reliability problems [7]. Such misfit dislocations have a high probability of intercepting the source and drain across the channel. Dopant diffusion from the source and drain could be enhanced along the defects, creating a weak buried channel. In this paper, we will apply TEM/STEM to investigate a few of these important issues: (1) the nature of various defects (threading dislocations, and misfit dislocations) and their evolution under thermal annealing; (2) the quality of SGOI and SSOI wafers
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and their thermal stability, with a focus on Ge diffusion and defect formation. TEM results will be correlated to the Raman data on the strain and strain degradation upon annealin
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