Ultrathin Dielectric Films Grown by Solid Phase Reaction of Pr with SiO 2
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Ultrathin Dielectric Films Grown by Solid Phase Reaction of Pr with SiO2 Hans-Joachim Müssig, Jarek Dąbrowski, Christian Wenger, Grzegorz Łupina, Roland Sorge, Peter Formanek, Peter Zaumseil, and Dieter Schmeißer1 IHP, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany 1 Angewandte Physik-Sensorik, BTU Cottbus, PF 10 13 44, D-03013 Cottbus, Germany ABSTRACT We have fabricated Pr-based high-k gate dielectric films by physical vapor deposition of metallic Pr on SiO2 under ultra-high vacuum (UHV) conditions at room temperature, followed by oxidation and annealing steps. The films have been analyzed by electrical measurements, X-ray Photoelectron Spectroscopy (XPS) and Transmission Electron Microscopy (TEM). Some insight into the physical processes involved has been obtained from ab initio calculations. The high-k gate stacks consist of a SiO2-based buffer with an enhanced dielectric constant and a Pr silicate barrier with a high dielectric constant. The role of the buffer is to preserve the high quality of the SiO2/Si(001) interface, and the role of the barrier is to keep the tunneling currents low by increasing its physical thickness. A Pr film deposited on a 1.8 nm SiO2 layer, oxidized at room temperature by air, and annealed in N2 atmosphere with O2 partial pressure of 10-3 mbar results in a stack with the Capacitance Equivalent Thickness of 1.5 nm and leakage of 10-4 A/cm2. INTRODUCTION Over the years, the requirements of the improved performance of microelectronics devices were met by continuous scaling of CMOS transistors. Each time the channel length is reduced, the SiO2 gate oxide has to be proportionally thinned in order to maintain a sufficiently high capacitance per gate unit area. As CMOS channel lengths continue to be scaled down to deep submicron dimensions, gate oxides thinner than 2 nm are needed [1]. In this regime, SiO2 is unable to provide effective insulation [2], since the direct tunneling increases exponentially with the decreasing thickness. To continue the scaling, alternative dielectrics with high dielectric constants (high-k) must be introduced. A thicker insulator with the dielectric constant higher than that of SiO2 may prevent carriers from tunneling while maintaining a high capacitance. These dielectrics are metal oxides or silicates. Pr2O3 is among the promising candidates to replace SiO2 [3]. A high-k material may be useful as a gate dielectric only when the density DIT of electrically active states at the channel interface is very low (1010/cm2). Interfacial states act as scattering centers (thus reducing the carrier mobility in the channel) and as a noise source (they trap and detrap the carriers at random). The interface between ultrathin SiO2 and Si(001) can be prepared to meet the industrial standards even if the SiO2 is as thin as 0.8 nm [4], but interfaces with high-k dielectrics have still a long way to go. Here we follow a temporary solution where the high-k material is grown on SiO2 buffer. The drawback is that the stack capacitance decreases, since the buffer ha
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