Understanding the relationship between Cu 2 ZnSn(S,Se) 4 material properties and device performance
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Understanding the relationship between Cu2ZnSn(S,Se)4 material properties and device performance Talia Gershon, Tayfun Gokmen, Oki Gunawan, Richard Haight, and Supratik Guha, IBM TJ Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598 Byungha Shin, KAIST Department of Materials Science, Munji-ro 14, Yuseong-gu, Daejeon, South Korea Address all correspondence to Talia Gershon at [email protected] (Received 29 September 2014; accepted 12 November 2014)
Abstract Cu2ZnSn(S,Se)4 (CZTSSe) photovoltaics (PV) have long been considered promising candidates for large-scale PV deployment due to the availability of constituent elements and steady improvements in device efficiency over time. The key limitation to high efficiency in this technology remains a deficit in the open-circuit voltage with respect to the band gap. The past decade has seen significant progress toward understanding how the various material properties such as bulk and surface composition, point defects (intrinsic and extrinsic), and grain boundaries all impact the optoelectronic properties of CZTSSe materials, and consequently device performance. This paper aims to summarize what is known about the CZTSSe bulk and surfaces, and how these material properties may be related to the Voc deficit.
Introduction The kesterite compound Cu2ZnSn(S,Se)4 (CZTSSe) has attracted widespread interest for many years due to its optimal band gap (1.0–1.5 eV, depending on the chalcogen composition), the earth-abundance of its constituent elements, and the hope that it may one day replace Cu(In,Ga)Se2 (CIGS) as a scalable commercial thin-film photovoltaic (PV) absorber material. Efficiencies have risen steadily to a certified champion value of 12.6% for the mixed sulfoselenide,[1] with demonstrated Jsc values reaching over 80% of the theoretical maximum. Meanwhile, the pure-selenide and pure-sulfide kesterites have reached record efficiencies of 11.6[2] and 9.2%,[3] respectively. However, the performance of CZTSSe devices still trails that of CIGS, largely due to a deficit in the open-circuit voltage (Voc), which also limits the fill factor.[4] There have been numerous hypotheses for what is presently limiting the device Voc. These can be grouped into three broad categories: a non-Ohmic back contact, a high degree of disorder and/or compensating defects in the CZTSSe bulk, and a poorly optimized interface with the buffer layer. The current champion CZTSSe device architecture is largely borrowed from CIGS technology, where a soda-lime glass substrate, Mo bottom contact, CdS buffer layer, and ZnO/ITO bilayer electrode have been found to yield the highest performance.[1] The full device stack is thus: glass/Mo/CZTSSe/CdS/ ZnO/ITO. We note that in high-efficiency CZTSSe devices, an interfacial Mo(S,Se)2 layer is always present between the Mo and the CZTSSe. This interfacial layer is believed to be important for film adhesion and also for ensuring Ohmic contact with CIGS.[5,6] However, it may not be true that this contact
is Ohmic for all CZTSSe ma
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