Viscoelastic Modeling and Reliability Assessment of Microelectronics Packages
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Viscoelastic Modeling and Reliability Assessment of Microelectronics Packages Aditya Karmarkar1, Charlie Zhai2, Xiaopeng Xu3, Xiao Lin3, Greg Rollins3 and Victor Moroz3 1
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Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh, India Silicon Operations, Nvidia, 2701 San Tomas Expressway, Santa Clara, CA 95050, USA 3 TCAD, Synopsys, Inc. 700 East Middlefield Road, Mountain View, CA 94043, USA
ABSTRACT Viscoelastic stress relaxation occurs at operating temperature in underfill materials of flip-chip packages with high power devices. Multi-level finite element analysis is performed to study the impact of the viscoelastic relaxation on package reliability. The stress simulations reveal that the relaxation in underfill material leads to higher stress concentration in solder bumps. The failure analysis shows that the induced high stress develops higher crack driving forces. The results demonstrate that the underfill material property such as viscosity can shift failure mode from die corner delamination to near bump delamination. Therefore, the numerical study can be used as a guideline to select underfill material for package reliability improvements. INTRODUCTION Flip-chip technology utilizes solder bumps and surrounding underfills to package silicon chip. The chip-package interaction (CPI) is a major reliability concern for flip-chip packages with fragile low-k or ultra low-k dielectrics that are adjacent to the bumps and underfills [1], [2]. Near bump and die corner delamination are the primary failure modes that are mitigated by selecting bump and underfill materials with lower thermal mismatch stress and higher strength [3], [4]. As the industry is required to move towards lead-free bumps, the choice of underfill materials needs to be reevaluated. It has been observed that underfill materials exhibit nonnegligible viscoelastic stress relaxation at operating temperature for high power devices. Viscoelastic relaxation in the underfill material may lead to stress redistribution and cause overloading and failure in the surrounding structures [5]. While in situ observation is lacking, numerical analysis is necessary to understand the failure mechanisms. In this study, an advanced process simulator is used for 3D package structure generation and for stress history tracking [6]. The viscoelastic relaxation of underfill material is simulated using Maxwell model and the model parameters are extracted from measured data [5], [6]. Submodeling technique is employed for global and local stress analyses and the J-integral method is used to calculate strain energy release rate. The simulation results are used to understand the failure mechanisms and to develop strategies for reliability improvements.
NUMERIC SIMULATIONS Mechanical stress simulations are performed for the package structure shown in Figure 1. The overall dimensions of the structure are 20mm×1.884mm×0.5mm, and it consists of a die, a layer of smear material, a substrate, solder bumps and the underfill material. The smear material represents the
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