Wafer Nanotopography Effects on CMP: Experimental Validation of Modeling Methods
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Wafer Nanotopography Effects on CMP: Experimental Validation of Modeling Methods Brian Lee1, Duane S. Boning1, Winthrop Baylies2, Noel Poduje3, Pat Hester3, Yong Xia3, John Valley4, Chris Koliopoulus4, Dale Hetherington5, HongJiang Sun6, Michael Lacy7 1
Massachusetts Institute of Technology, Cambridge MA BayTech Group, Weston MA 3 ADE Corporation, Westwood MA 4 ADE Phase-Shift, Tucson AZ 5 Sandia National Laboratories, Albuquerque NM 6 Philips Semiconductor, Albuquerque NM 7 Lam Research, Fremont CA 2
ABSTRACT Nanotopography refers to 10-100 nm surface height variations that exist on a lateral millimeter length scale on unpatterned silicon wafers. Chemical mechanical polishing (CMP) of deposited or grown films (e.g., oxide or nitride) on such wafers can generate undesirable film thinning which can be of substantial concern in shallow trench isolation (STI) manufacturability. Proper simulation of the effect of nanotopography on post-CMP film thickness is needed to help in the measurement, analysis, diagnosis, and correction of potential problems. Our previous work has focused on modeling approaches that seek to capture the thinning and post-CMP film thickness variation that results from nanotopography, using different modeling approaches. The importance of relative length scale of the CMP process used (planarization length) to the length scale of the nanotopography on the wafer (nanotopography length) has been suggested. In this work, we report on extensive experiments using sets of 200 mm epi wafers with a variety of nanotopography signatures (i.e., different nanotopography lengths), and CMP processes of various planarization lengths. Experimental results indicate a clear relationship between the relative scales of planarization length and nanotopography length: when the planarization length is less than the nanotopography length, little thinning occurs; when the CMP process has a larger planarization length, surface height variations are transferred into thin film thickness variations. In addition to presenting these experimental results, modeling of the nanotopography effect on dielectric CMP processes is reviewed, and measurement data from the experiments are compared to model predictions. Results show a good correlation between the model prediction and the experimental data. INTRODUCTION Nanotopography (height variations of 20 to 80 nm that exists over lateral distances of several millimeters) on unpatterned silicon wafers is becoming a serious issue in IC fabrication [1]. One principal concern is the interaction of nanotopography with long planarization length CMP processes that creates undesired thinning of surface films, which may lead to yield concerns in shallow trench isolation processing [6]. This work reports on the results of a set of experiments performed on 200mm epi wafers, which are divided into wafer types that exhibit distinct and identifiable nanotopography characteristics. Wafer sets, consisting of samples of each wafer type, are run on a variety of CMP procM4.9.1
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