Nanotopography Issues in Shallow Trench Isolation CMP
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Nanotopography
Issues in Shallow Trench Isolation CMP
Duane Boning and Brian Lee Abstract As advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important concern in shallow trench isolation (STI) on wafers polished by means of chemical–mechanical planarization (CMP). Previous work has shown that nanotopography—small surface-height variations of 10–100 nm in amplitude extending across millimeter-scale lateral distances on virgin wafers—can result in CMP-induced localized thinning of surface films such as the oxides or nitrides used in STI. A contact-wear CMP model can be employed to produce maps of regions on a given starting wafer that are prone to particular STI failures, such as the lack of complete clearing of the oxide in low spots and excessive erosion of nitride layers in high spots on the wafer. Stiffer CMP pads result in increased nitride thinning. A chip-scale pattern-dependent CMP simulation shows that substantial additional dishing and erosion occur because of the overpolishing time required due to nanotopography. Projections indicate that nanotopography height specifications will likely need to decrease in order to scale with smaller feature sizes in future IC technologies. Keywords: chemical–mechanical planarization, chemical–mechanical polishing, CMP, contact-wear simulation, nanotopography, shallow trench isolation (STI), silicon wafers.
been deposited into the trench, which also results in overburden oxide above the nitride active areas. In the ideal CMP process, the oxide is removed completely in all active regions, leaving oxide only in the trench regions (Figure 3b). Three key failure mechanisms may arise, however, as shown in Figures 3c–3e. First, the CMP process may fail to completely clear the overburden oxide. Second, the process may succeed in clearing the oxide, but result in an excessive removal (erosion) of the nitride film. Finally, excessive removal of the oxide (dishing) within the trench may occur. In this review, we focus on how nanotopography may exacerbate these STI CMP failure mechanisms. We first summarize a simulation methodology that can be used to understand how a wafer surface with underlying nanotopography will evolve during CMP. A blanket wafer simulation, using an unpatterned wafer with a conformal (“blanket”) film layer, is then used to study the first two failure mechanisms. Finally, additional dishing and erosion in patterned STI wafers due to nanotopography are simulated, using a pattern-dependent STI CMP model.
Contact-Wear Model for Nanotopography/CMP Interaction Our first goal is to understand how nanotopography across large regions of the wafer (here, the center 100-mm region of a wafer is simulated) affects the polishing of a blanket oxide/nitride film stack, as illustrated in Figure 4. A variety of modeling approaches have been proposed to convert initial wafer nanotopography to final post-CMP film-thickness information, including statistical measures,5 simple scal-
Introduction Nanotopography is
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