3D Thermal Stress Models for Single Chip SiC Power Sub-Modules
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1069-D12-02
3D Thermal Stress Models for Single Chip SiC Power Sub-Modules Bang-Hung Tsao1, Jacob Lawson1, and James Scofield2 1 University of Dayton Reserach Institute, 300 College Park, Dayton, OH, 45469-0074 2 Air Force Reserach Labratory, WPAFB, OH, 45433 ABSTRACT Three dimensional models of single chip SiC power sub-modules were generated using ANSYS in order to simulate the effects of various substrate materials, heat fluxes, and heat transfer coefficients on temperature and thermal stress contours. Silicon nitride, aluminumnitride, alumina were compared as substrates with or without an additional layer of CVD diamond on either top or bottom of the surfaces. Simulated heat fluxes of 100 to 300 watts/cm2 resulted in device junction temperatures in the range of 359 to 7289 K. With modest cooling, represented by a heat transfer coefficient (hconv) of 3350 watts/m2-K, SiC chips operated at 300 watts/cm2 power density maintained junction temperatures Tj < 688 K. In the applied heat flux range, the maximum Von Mises stress of a simulated single SiC device sub-module was between 767 MPa to 54.9 GPa. Whereas, the maximum shear stress was between 153 MPa and 8.1 GPa. Regardless of stacking configuration, the maximum chip temperature, Von Mises stress, and shear stress decreased with increasing heat transfer coefficient from 50 to 5000 watts/m2-K. If consistent with simulation results, CVD diamond integrated substrates should be superior in most cases to those comprised of only AlN, Al2O3, and Si3N4. Experimental validation of ANSYS results and more extensive multiple-chip power module simulations will be explored. INTRODUCTION SiC is an excellent candidate for modern power electronics due to its superior breakdown voltage, thermal conductivity, and inherent resistance to radiation and chemical attack [1]. Discrete SiC devices have many advantages, most notably, reduced switching losses, high voltage, and high temperature capability [2]. As a result, the use of SiC devices can increase system efficiency and reduce volume and weight. Though a SiC switch module potentially requires less cooling and offers increased reliability, power module failure mechanisms tend to be thermally activated or enhanced [3]. These thermo-mechanical failure modes are expected to be significantly accelerated under some of the high temperature operating conditions projected for SiC power electronic devices. The objective of this study was to use ANSYS [4] finite element analysis (FEA) to predict temperature and stress distributions for notional SiC power module geometries under various loading and environmental conditions to be subsequently validated by experiment. EXPERIMENT This study began with the generation of highly simplified stacking configuration geometries representative of a partial power sub-module using ANSYS FEA software. As seen in Figure 1 three basic stacking configurations were chosen. All three geometries begin with SiC as the top layer, representative of a generic “device”. The second material in the stack is a thin layer
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