Pre-Applied Inter Chip Fill Material and Process for Advanced 3D Chip Stack
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Pre-Applied Inter Chip Fill Material and Process for Advanced 3D Chip Stack Akihiro Horibe and Fumiaki Yamada Association of Super-Advanced Electronics Technologies 1-28-38, Shinkawa, Chuo-ku, Tokyo 104-0033 Japan ABSTRACT To pursue further performance improvement of semiconductor devices, threedimensional (3D) chip integration using TSV would be one of the key technologies. Inter Chip Fill (ICF), resin to fill gaps between chips, would be an important component for highly reliable and durable 3D integrated devices. Technology using the pre-applied ICF, designed for advanced 3D chip-stack with narrow gap of less than 10um-pitch TSV connections, was developed and successful stack of chips was demonstrated. This paper describes the characteristics of the fill resin material, process conditions required for the stack joining and the cause of mechanical stress within the stacked chip and required material features of the pre-applied ICF and device structure to reduce the stress. INTRODUCTION Improvement of computation and network performance so far, has been realized by the improvement of the performance of integrated circuits realized by the scaling down (miniaturization of) the transistor and wiring size, further miniaturization has become more and more difficult due to the increase of the cost of fabrication and the device variation. Therefore, 3D integration is expected to be key technology for future improvement [1]. 3D integration makes it possible to increase the data bandwidth with low line driving power by reducing the parasitic capacitance due to the shorter data communication distance, and by lowering the data rate due to increased number of interconnects between the stacked semiconductor chips. There are some 3D integration processes such as wafer level integration and chip level integration. The chip level integration has an advantage for assembly process which allows the stacking of KGDs (Known-Good-Dies) with different sizes. An ICF resin is applied to layers between chips as shown in Figure 1. The ICF material and stacking process must be optimized for joining yield, thermo-mechanical stress reduction. Capillary process, commonly used for chip stacking in current flip chip packaging, and pre-applied process, for filling resin into such layers, are compared in Table 1. Smaller bumps for fine pitch interconnects for narrow gap design between stacked chips, might reduce heat resistance and thermo-mechanical stress [2][3], however, require a new resin filling and deoxidization processes due to the small gap. The new “Stack Joining process” using pre-applied resin, which we previously proposed [4], enables 3D multi chip joining at one time instead of sequential chip-by-chip joining. In this process, multiple chips were aligned and temporarily stacked sequentially using the adhesivity of ICF at temperature between melting point of half cured (B-staged) resin and polymerization temperature, and finally all metal bumps of stacked chips are melted and joined together. This process can substantially r
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