A 12-bit branching time-to-digital converter with power saving features and digital based resolution tuning for PVT vari
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A 12-bit branching time-to-digital converter with power saving features and digital based resolution tuning for PVT variations Jian Sen Teh1
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Liter Siek1
Received: 26 July 2019 / Revised: 8 May 2020 / Accepted: 15 June 2020 Ó Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract This paper presents a 12-bit branching Time-to-Digital converter (TDC) fabricated in a 40 nm CMOS technology. It composes of a 6-bit coarse counter TDC, and a 6-bit fine TDC. The fine TDC utilizes a proposed branching technique to interpolate between the phases of a 16-stage gated ring oscillator, increasing its number of phases from 16 to 64. Therefore, the TDC resolution is improved to be 4 times finer. The TDC incorporates fully digital based resolution tuning capability that enables its resolution to be more stable over PVT variations. Measurement results show that the resolution tuning reduces the resolution variation by 92.3% over a temperature range of - 40 to 125 °C. However, the simple resolution tuning method causes the TDC to have a relatively large resolution of 36.2 ps. The trade-offs between TDC resolution, yield, and scalability are discussed. The proposed TDC uses simple gated inverters based samplers instead of conventional arbiters to reduce power and area consumption. In addition, power gating features of the proposed TDC enable a low power consumption of 275 lW at a sampling rate of 5 MS/s. Without any linearity calibrations, the TDC DNL, INL, single-shot precision, and figure-of-merit are measured to be 1.30 LSB, 3.61 LSB, 0.75 LSB, and 61.9 fJ/conv.-step, respectively. Keywords Branching Bridging capacitors Coarse-fine Gated inverters based sampler Phase interpolation Power gating Resolution tuning Time-to-digital converter TDC
1 Introduction Time-to-Digital converters (TDC) are traditionally used for time-of-flight measurements [1, 2]. Due to their highly digital nature, TDCs have the ability to benefit from and scale with advancing technology. Hence, their usage have become increasingly popular in recent years where they have been applied in several mixed signal systems. They have been used for jitter measurements [3, 4]. They have also replaced phase-frequency detectors in phase-locked loops (PLL) to form digital or all-digital PLLs [5–9]. They can also form time-mode Analog-to-Digital converters (ADC) using Voltage-to-Time converters [10–15]. TDCs quantize an input time difference, Tin , into its digital representation. The simplest and fastest TDC is the & Jian Sen Teh [email protected] 1
Centre of Excellence in IC Design (VIRTUS), Nanyang Technological University, 50 Nanyang Ave, Singapore 639798, Singapore
flash or delay line TDC [1]. It quantizes Tin in terms of the unit delay cell in a delay line. Although simple, its time resolution, TLSB , is limited by the technology which determines the minimum delay of the unit delay cell. Several TDC architectures have been proposed to achieve finer resolutions. Vernier delay lines TDCs [3, 16–20] can achieve fine resoluti
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