Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio App
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Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications Prateek Sikka1
· Abhijit R. Asati1 · Chandra Shekhar1
Received: 12 November 2019 / Revised: 11 November 2020 / Accepted: 13 November 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract In digital signal processing, digital down converters (DDCs) convert digitized, bandlimited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and areaoptimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application. Keywords Hardware description language (HDL) · High-level synthesis (HLS) · Field programmable gate array (FPGA) · Software-defined radio · Vivado HLS · MATLAB HDL coder
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Prateek Sikka [email protected]
Extended author information available on the last page of the article
Circuits, Systems, and Signal Processing
1 Introduction In modern communication systems, digital down converters (DDCs) are essential for transforming intermediate frequency (IF) signals to baseband frequencies. DDCs with input signal bandwidths above 1 MHz are known as wideband DDCs, whereas those with less than 1 MHz bandwidth are known as narrow-band DDCs. Wideband DDCs are typically used in applications such as 4GMax and satellite communications, whereas narrow-band DDCs have applications in commercial broadcast. With the growing complexity of modern digital designs and in a bid to enable pre-silicon testing and SW development, field programmable gate arrays (FPGAs) are also becoming popular for VLSI design flow. In addition, because they are reconfigurable, they allow designers and architects to have ea
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