A 6-bit hierarchal TDC architecture for time-based ADCs
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A 6-bit hierarchal TDC architecture for time-based ADCs Mostafa Rashdan1 Received: 27 March 2020 / Revised: 21 August 2020 / Accepted: 8 October 2020 Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract A 6-bit hieratical time-to-digital (TDC) architecture suitable for time-based ADC circuits is presented in this paper. The design consists of similar stages at which each stage recovers one bit. Using the proposed architecture, the total number of bits can be increased without complicating the design as in other conventional TDC architectures. A 6-bit 1.3 Gb/s TDC circuit has been designed and simulated in 28 nm mixed-signal CMOS technology based on the proposed architecture using 5.6 ps time resolution. A Calibration circuit has been designed for each delay line in order to tolerate the variations due to process and mismatch between transistors, which affect the designed delay lines in the design. Monte-Carlo simulations have been done to the designed TDC before and after using the calibration circuit. The calibration circuit corrects the delay line values with an error of ± 2%. The INL and the DNL accuracy of the designed TDC are less than 0.5 LSB and 0.4 LSB. The power consumption of the designed 6-bit TDC circuit is less than 1.3 mW including the calibration circuits. Keywords Time-based architectures Hierarchal TDC High resolution Time-based ADC
1 Introduction TDC circuits are used to convert the time difference between two signals into a digital code. They are used in different applications such as digital phase-locked-loop (DPLL) circuits [1, 2], Time-based data converters such as time-based analog to digital converters (ADCs) [3, 4], serial data transmission [5, 6] and positron-emission tomography (PET) imaging systems [7]. In DPLL, TDC is used to convert the phase error into a digital code that can be used to correct the frequency of the output signal. The DPLL is needed to be easily and precisely programmable to achieve the requirements for high speed applications, which is difficult to be achieved by analog PLL. The resolution of the TDC defines how precise the DPLL can reach. In Time-based ADCs, the circuit consists of two blocks, a voltage-to-time circuit (VTC) followed by a TDC circuit. The total number of bits of the TDC circuit defines the resolution of the ADC. TDC with
& Mostafa Rashdan [email protected] 1
Faculty of Energy Engineering, Aswan University, Aswaˆn, Egypt
high number of bits is needed to achieve high resolution ADCs. TDC-based receivers are used in time-based serial transmission. With the increase of data rate, the demand for high-speed serial links has been increased. High number of bits TDC circuits are needed to transmit a high number of bits with high data rate. TDC circuits are used also in medical applications such as PET imaging systems, the TDC is used to measure the time difference between two physical events. The accuracy of the measurement is based on the total number of bits of the TDC circuit. Different TDC architectures have been pub
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