Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications
This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The aut
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Taimur Rabuske Jorge Fernandes
Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications
Analog Circuits and Signal Processing Series editors Mohammed Ismail, Dublin, USA Mohamad Sawan, Montreal, Canada
More information about this series at http://www.springer.com/series/7381
Taimur Rabuske • Jorge Fernandes
Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications
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Taimur Rabuske INESC-ID Instituto Superior Técnico Universidade de Lisboa Lisboa, Portugal
Jorge Fernandes INESC-ID Instituto Superior Técnico Universidade de Lisboa Lisboa, Portugal
ISSN 1872-082X ISSN 2197-1854 (electronic) Analog Circuits and Signal Processing ISBN 978-3-319-39623-1 ISBN 978-3-319-39624-8 (eBook) DOI 10.1007/978-3-319-39624-8 Library of Congress Control Number: 2016942569 © Springer International Publishing Switzerland 2017 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer International Publishing AG Switzerland
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Preface
The integrated successive-approximation-register (SAR) analog-to-digital converter (ADC) is known to present a remarkable energy efficiency. Additionally, the SAR ADC is a very scaling-friendly architecture, due to its highly digital and switching-intensive nature and its ability to effortlessly accommodate rail-to-rail signals without resorting to precision amplifiers. These characteristics have been boosting the popularity of SAR ADCs as process scaling reduces the transistor’s intrinsic gain and supply voltages. The most basic form of an SAR ADC requires a voltage comparator, a digital controller, a track-and-hold (TH) circuitry, and a digital-to-analog converter (DAC). In most of the reported designs, the DAC of an SAR ADC is capacitive and relies on the charge-redistribution (CR) principle. Alternatively, an SAR ADC that relies on the charge-sharing (CS) principle has been proposed more recently. The main advantages
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