A catalytic alloy approach for graphene on epitaxial SiC on silicon wafers
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Ryan Brock and Reinhold H. Dauskardt Department of Materials Science and Engineering, Stanford University, Stanford, California 94305, USA
Barry Wood Centre for Microscopy and Microanalysis, The University of Queensland, St. Lucia, Queensland 4072, Australia
John Boeckl Materials and Manufacturing Directorate, Air Force Research Laboratories, Wright-Patterson AFB, Ohio 45433, USA (Received 7 July 2014; accepted 1 January 2015)
We introduce a novel approach to the synthesis of high-quality and highly uniform few-layer graphene on silicon wafers, based on solid source growth from epitaxial 3C-SiC films. Using a Ni/Cu catalytic alloy, we obtain a transfer-free bilayer graphene directly on Si(100) wafers, at temperatures potentially compatible with conventional semiconductor processing. The graphene covers uniformly a 20 silicon wafer, with a Raman ID/IG band ratio as low as 0.5, indicative of a low defectivity material. The sheet resistance of the graphene is as low as 25 X/square, and its adhesion energy to the underlying substrate is substantially higher than transferred graphene. This work opens the avenue for the true wafer-level fabrication of microdevices comprising graphene functional layers. Specifically, we suggest that exceptional conduction qualifies this graphene as a metal replacement for MEMS and advanced on-chip interconnects with ultimate scalability.
I. INTRODUCTION
Ever since graphene was experimentally isolated about a decade ago,1 the high temperature (1300–1700 °C) Si sublimation from crystalline silicon carbide (SiC) bulk substrates has been extensively regarded as the cleanest and most controlled means of obtaining quality graphene at the wafer level.2–4 However, the transfer of this approach to its natural pseudo-substrate, i.e., epitaxial SiC films on silicon,5–7 has lagged behind despite being strongly driven by substantial cost (SiC wafers are about 100 times more expensive than silicon) and large-scale fabrication arguments. This endeavor has proved more challenging than expected, in particular, because of the upper limit set by the melting temperature of silicon and the scarce availability of a defect-free and atomically smooth epitaxial SiC on Si(111) starting template.8,9 In response to such challenges, we have recently demonstrated an alternate approach to the wafer-level, transfer-free uniform synthesis of graphene on silicon.10 As for the sublimation process, our new methodology relies on the use of epitaxial SiC on silicon as a solid source of carbon. The main advantage of this approach is Contributing Editor: Mauricio Terrones a) Address all correspondence to this author. e-mail: f.iacopi@griffith.edu.au This paper has been selected as an Invited Feature Paper. DOI: 10.1557/jmr.2015.3 J. Mater. Res., Vol. 30, No. 5, Mar 14, 2015
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that it enables a wafer-scale patterned synthesis of graphene by prepatterning of the source SiC layer.10,11 However, our catalyst-mediated process10 allows for a reduction in the optimal synthesis tempe
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