A Comparison of N+ Type and P+ Type Polysilicon Gate in High Speed Non-Volatile Memories
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A Comparison of N+ Type and P+ Type Polysilicon Gate in High Speed Non-Volatile Memories Moon Kyung Kim1, SooDoo Chae2, Chung Woo Kim2, Jo-won Lee3, and Sandip Tiwari1 1 Electrical and Computer Engineering, Cornell University, Ithaca, NY, 14850 2 Semiconductor Business, Samsung Electronics Co., Yongin-City, Kyunggi-Do, Korea, Republic of 3 Tera-level Nano Devices, Seoul, Korea, Republic of ABSTRACT The polarity of gates and the threshold voltages are primary parameters that determine the electric fields in the gate stack region of non-volatile memories. This field is central to programming, retention and the other characteristics of the devices. We have investigated the effect of the gate polysilicon polarity, experimentally, for silicon-oxide-nitride-oxide-silicon (SONOS) memory devices on silicon-on-insulator (SOI) wafers. An ultra-thin oxide-nitrideoxide (ONO) film with high trap density and strong localization of the trapping provides the scalability and retention in our structures. The effect of ONO film, grown and deposited and of doping was simulated and characterized. Retention is affected by the electric field between the control gate and the storage node. Our experiments and simulations verify the consequences of different polarity of control gates through the change in electric field that they cause in retention and erase times for n+ and p+ polysilicon gate SONOS memories is verified through the characteristic energies of the processes.
INTRODUCTION There is broad consensus that achieving both the reliability and low voltages of operation is a very difficult challenge for the floating gate type EEPROM as the gate lengths shrink [1]. The floating-gate-type EEPROM requires a thicker tunneling oxide of more than 7-9 nm to guarantee retention characteristics by suppressing tunneling. This gives rise to a high-voltage operation necessitated by a 6 MV/cm of programming/erase electric fields [2]. Use of distributed storage, thus reducing consequences of leakage paths, is one of the ways of addressing these problems. Advanced thin film technology has resulted in a low voltage operation and long retention characteristics in devices based on Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) [3][4]. Silicon nitride and its interface with silicon dioxide provides an alternative for this charge storage where the highly localized storage of charge at increased number of sites may allow a further scaling of the insulator thickness and a trade-off in other attributes. But, SONOS memory has problems in discharging of the electrons from the traps of silicon nitride. When SONOS memory is discharged, the electrons from a gate electrode are injected into silicon nitride through the top oxide stack. To resolve this problem, we have used p+ polysilicon gate, which has a higher work function than n+ polysilicon gate. This decreases the amount of back-tunneling electrons from the gate. In our experiments, the effect of doping levels has been simulated and characterized.
EXPERIMENT Figure 1 shows schematic views of n+ t
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