• PDF / 1,312,017 Bytes
• 9 Pages / 612 x 792 pts (letter) Page_size
• 84 Downloads / 222 Views

DOWNLOAD

REPORT

---

1066-A08-02

Floating-Gate a-Si:H TFT Nonvolatile Memories Yue Kuo, and Helinda Nominanda Thin Film Nano & Microelectronics Research Laboratory, Texas A&M University, College Station, TX, 77843-3122 Abstract Charge and discharge phenomena of the floating-gate amorphous silicon thin film transistor have been studied under dynamic operation conditions. The charge storage capacity decreases with the increase of the drain voltage because it is easier for electrons to be transported to the drain electrode than to be injected into the gate dielectric layer. The discharge efficiency with respect to the drain voltage has been investigated using three different discharge methods: negative gate bias voltage, light exposure, and thermal annealing, separately. The channel length affected both the charge capacity and the discharge efficiency due to the charge storage mechanism and the channel resistance. Majority of the stored charges were removed with the above method through various mechanisms. The low temperature favors the charge storage but the high temperature favors the discharge. This study revealed key parameters for the optimum operation of the low temperature fabricated nonvolatile memory device. Introduction A charge storing device based on embedding a thin layer of hydrogenated amorphous in the gate dielectric of a hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) had been demonstrated recently [1,2]. The TFT’s modified gate dielectric consisted of a sandwich of bottom silicon nitride (SiNx) as the control dielectric, a-Si:H as the floating gate, and top SiNx as the tunnel dielectric. The magnitude and polarity of the gate voltage (Vg) control the behavior of charges injected into and released from the a-Si:H floating gate. Memory characteristics could be estimated from the hysteresis of transfer characteristic curves [1,2]. This kind of memory device is attractive for applications on flexible substrates, displays, sensors, etc., due to its low temperature fabrication process. In this study, authors report the charging and discharging efficiency of the TFT memory under gate and drain bias using different methods such as opposite Vg stress, light exposure, and thermal annealing. Recently, the charge and discharge efficiencies of the TFT under the source and drain grounded condition were reported [3]. However, for many practical applications, the drain electrode is not grounded. Therefore, it is desirable to know the charge and discharge characteristics with the drain electrode biased. In this paper, authors investigated the charge storage capability and the discharge efficiency under the above condition. Mechanisms of both processes were also investigated. Experimental Figure 1 shows the cross-sectional view of a floating-gate a-Si:H TFT fabricated on a Corning 1737 glass substrate. The complete self-aligned TFTs were prepared with 2

photomasks [4]. The plasma deposition and etching processes are the same as those used in preparing a conventional a-Si:H TFTs with field effect mobility > 0.3 cm2/V-s a