A Dimple-Array Interconnect Technique for Power Semiconductor Devices
- PDF / 381,715 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 72 Downloads / 180 Views
A DIMPLE-ARRAY INTERCONNECT TECHNIQUE FOR POWER SEMICONDUCTOR DEVICES Simon S. Wen, Daniel Huff, and Guo-Quan Lu Power Electronics Packaging Laboratory Center for Power Electronics Systems The Bradley Department of Electrical and Computer Engineering Department of Materials Science and Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 24061 USA Phone: 1-540-231-3233 Email: [email protected]
ABSTRACT This paper describes a wireless-bond interconnect technique, termed Dimple-Array Interconnect (DAI) technique for packaging power devices. Electrical connections onto the devices are established by soldering arrays of dimples pre-formed on a metal sheet. Preliminary experimental and analytical results demonstrated potential advantages of this technique such as reduced parasitic noises, improved heat dissipation, as well as lowered processing complexity, compared to the conventional wire bonding technology in power module manufacturing. Thermomechanical analysis using thermal cycling test and FEM were also performed to evaluate the reliability characteristics of this interconnect technique for power devices.
metal interconnect/flex is then solder-attached to the devices. As shown in Fig. 1, the key feature of DAI is its dimpled metal interconnects which are convex valleys on metal sheet protruding from one side to enable easy forming of joints with underlying solderable devices through a solder layer. The resultant smooth fillets in solder bumps could significantly reduce thermally induced stresses and strains.
I. INTRODUCTION Research and development efforts in power electronics packaging have enabled ever-increasing levels of functional integration in power packages. Recent developments in three-dimensional packaging of power electronics modules have led to a variety of power device interconnect techniques, such as the ThinPak technology by the Silicon Power Corporation [1], the Power Overlay technology by General Electric company [2][3], the bottom-less flip chip technique by Fairchild Semiconductor [4], and the Metal Post Interconnected-Parallel Plate Structure (MPIPPS) [5], Embedded Power [6] and Flip Chip [7] techniques developed by the Center for Power Electronics Systems (CPES). These alternative approaches represent the latest progress in improving electrical performance, thermal management, and thermo-mechanical reliability of power packages and modules. Apparently, it is the cost and reliability that will ultimately determine which of the above technologies will set a major impact. Aiming at enhancing thermal fatigue reliability of solder bumping interconnect in power packaging application, we have developed the Dimple-Array Interconnect technique (DAI). DAI packaging involves the use of copper flex/sheet with arrays of pre-formed dimples, which serve as both electrical interconnections and heat dissipation paths. The
Figure 1. The cross section of Dimple Array Interconnect structure. In this paper, design and fabrication of a power IGBT module packaged by a Dimple-Array Interconnect
Data Loading...
