Low Power Interconnect Design
This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal
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Low Power Interconnect Design
Low Power Interconnect Design
Sandeep Saini
Low Power Interconnect Design
123
Sandeep Saini The LNM Institute of Information Technology Jaipur, Rajasthan, India
ISBN 978-1-4614-1322-6 ISBN 978-1-4614-1323-3 (eBook) DOI 10.1007/978-1-4614-1323-3 Library of Congress Control Number: 2014952901 Springer New York Heidelberg Dordrecht London © Springer Science+Business Media New York 2015 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper Springer Science+Business Media LLC New York is part of Springer Science+Business Media (www. springer.com)
Dedicated to my parents and my wife Manpreet Kaur
Preface
Motivation In deep sub-micron (DSM) technologies, interconnects no longer behave as resistors but may have associated parasitics such as capacitance and inductance. With a linear increase in interconnect length, both the interconnect capacitance (C) and interconnect resistance (R) increase linearly, making the RC delay increase quadratically. With the continuous trend of very large scale integration (VLSI) technology scaling and frequency increasing, interconnect delay becomes a significant bottleneck in system performance. From international technology roadmap for semiconductors (ITRS) projection, interconnect delay can contribute to more than 50 % of the delay when the feature size is beyond 180 nm. As a result, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high performance designs. Although the RC delay is not a precise measure of the time necessary for a signal to propagate through a wire, the total RC delay of a section of a line may be useful as a figure of merit. In order to increase the operating speed of an integrated circuit, it is necessary to reduce the RC delay. In addition to increased signal propagation delay, increased power dissipation is another effect of large interconnect impedance. The total RC delay of an interconnect line can be reduced
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