A Low-Cost BiCMOS Process with Metal Gates
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A Low-Cost BiCMOS Process with Metal Gates
H.W. van Zeijl, and L.K. Nanver Laboratory of ECTM, DIMES, Delft University of Technology P.O.Box 5053, 2600 GB, Delft, The Netherlands Phone: +31 15 2784949 Fax: +31 15 2622163 E-mail: [email protected]
ABSTRACT A low-complexity and low-cost double-metal BiCMOS process is proposed with only 13 mask steps. By decoupling the source-drain thermal budget from gate-stack formation, metal gates are realizable.
INTRODUCTION Scaling BiCMOS technology will in general increase the process complexity and reduce the process flexibility. Together with the increasing costs of an advanced process line, research related to such technology can become forbiddingly expensive. The research capabilities are also compromised by high process complexity, which reduces the compatibility with alternative processing modules, for example for the integration of specialized electronic components and smart sensors [1]. This work proposes a novel device architecture that enables submicron device dimensions but maintains a moderate process complexity that moreover allows an attractive degree of flexibility. Significant process simplification is achieved because the process flow mainly contains steps that are common to both the bipolar and the CMOS device formation. A key point is the decoupling of the thermal budget of source-drain formation from the gate-stack formation while still maintaining a self-aligned device structure. This gives an extra degree of freedom in the selection of both the gate dielectric and the gate electrode material, thus making this structure very suitable as a research vehicle for the study of alternative gate stacks. The total process presented here is a 13 mask double-metal BiCMOS process that can be fabricated with conventional process equipment. It features high frequency BJT’s and metal gate MOS devices.
PROCESS DESCRIPTION The BiCMOS process flow is show schematically in figure 1. First a 0.9 µm epitaxial silicon layer is grown on a p-type (100) substrate with implanted buried n+ layers. The dopant concentration in the epitaxial layer is 1016 cm-3 and serves as collector for the NPN and as n-well. Next a high-energy, high-dose phosphorus implant is performed to form the collector plug. A high-energy, high-dose boron implant contacts the substrate and provides junction isolation for the bipolar transistors. The collector plug and p-isolation also contact the n-well and p-well, respectively, and are used as channel stopper. The p-well is formed by a high-energy, low-dose
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boron implantation that gives a dopant concentration of 1017 cm-3. A 200 nm low-stress silicon nitride film (SiNx, x=0.94) is deposited directly on the silicon by LPCVD (field nitride). In the active device areas the field nitride is plasma etched followed by a thermal oxidation of 20 nm of silicon dioxide. Next a 200 nm thick polysilicon film is deposited. This film is heavily doped by ion implantation: boron is implanted above the PMOS and the NPN’s and phosphorus above the NMOS. A 200 nm
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