Investigation of the Growth and Chemical Stability of Composite Metal Gates on Ultra-thin Gate Dielectrics
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resistivity and chemical stability. In contrast, many pure metals react with SiO 2 at elevated temperatures 3' 4 . However, few fundamental studies of the growth at the monolayer level and chemical stability of these compound metals on Si0 2 or other advanced gate dielectrics such as 57 Si0 2/Si 3N4 (ON) stacks have been conducted ' . This work uses on-line Auger electron spectroscopy (AES) to investigate the initial stages of growth of reactively sputtered TiNx and WNx films on ultra-thin SiO 2 and ON stack dielectrics prepared by remote plasma enhanced chemical vapor deposition (RPECVD). The chemical stability of these compound metal/dielectric interfaces after on-line rapid thermal annealing (RTA) treatments up to 850 'C is also monitored by AES. Finally, to demonstrate the performance of these compound metals as gate electrodes, standard high frequency and quasistatic capacitance-voltage (C-V) measurements were conducted on MOS capacitors using TiNx or WNx gates and conventional thermal SiO 2 gate dielectrics. EXPERIMENT Ultra-thin SiO 2 or ON dielectrics were prepared by RPECVD on 3 in. Si (100) wafers as previously described 6 and were measured by AES. Samples with ON dielectrics resulted in a Si/Si0 2/Si3N4 stack structure and formation of a metal/Si 3N4 interface. To observe the initial stages of metal growth, several ultra-thin layers of TiN, or WN, were sequentially deposited5 on the dielectrics at 300 K by reactive DC magnetron sputtering and AES spectra collected. For a 171
Mat. Res. Soc. Symp. Proc. Vol. 532 © 1998 Materials Research Society
8 metal thickness greater than about 0.8 nm the SiLvv AES peak is suppressed , indicating that the interface is buried. Thicker metal layers (0.5 - 1.0 nm each) were then deposited to observe the development of bulk characteristics. Chemical stability of the TiN,/Si0 2, TiN,/Si 3N4, WNl/Si0 2 , and WN,/Si 3N 4 interfaces was studied by on-line RTA. For each dielectric, a 0.6 - 0.8 nm thick metal layer was deposited to bury the interface. For this thickness of metal, changes in the SiLvv AES peak following RTA treatments provide a sensitive probe of the metal/dielectric interface. Each sample was subjected to sequential 3 min. RTA treatments in vacuum from 350 'C to 850 'C (750 'C for WNx). AES spectra were recorded following each anneal. MOS capacitors were fabricated 5 using a conventional 7.5 nm thermal Si0 2 gate dielectric and TiNx or WNx metal gates. Standard high-frequency and quasi-static C-V measurements were conducted to determine the electronic properties of these devices.
RESULTS AND DISCUSSION In Figs. la and Ib, a series of AES derivative spectra are shown which detail the interrupted growth of TiN, on Si0 2 and ON dielectrics respectively. The relevant spectral features are labeled according to the Auger transitions which produce them. In each figure, the bottom curve shows the spectrum for the bare dielectric. Subsequent curves are offset in proportion to the integrated TiN, deposition time, as indicated on the right-hand axis. For both figures, t
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