Influence of In-Situ Arsenic Doped Emitter Poly Process Conditions on RF-BiCMOS Device Parametrics
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1108-A13-03
Influence of In-Situ Arsenic Doped Emitter Poly Process Conditions on RF-BiCMOS Device Parametrics Richard Egloff 1, Namwoong Paik 1, Susan Beckett 1, Dan Codi 1, Jerry Mase 1 and Wayne Tomassi 1. 1
NXP Semiconductors, Hopewell Junction, NY 12533
ABSTRACT This paper discusses the influence of deposition conditions on in-situ As doped amorphous silicon emitter films used in NPN RF bipolar transistors. In-situ As doped amorphous and/or polysilicon layers improve electrical performance in BiCMOS devices by reducing the number of process steps and eliminating issues associated with implanted polysilicon on high aspect ratio topographies (plug effect). This study was made using a vertical furnace configuration capable of 150 wafer loads. Because adsorbed AsH3 decomposition species tightly bind to the active surface sites and inhibit the deposition rate, the process recipe is complex. Predictable bipolar parametrics require control of the As diffusion profile within the base region after activation, so a thorough understanding of emitter film growth and dopant incorporation is necessary. We describe the relationship between process conditions and recipe variants on transistor gain (Hfe), base current (Ib), and emitter resistance (Re). SIMS and in-line sheet resistivity measurements were used to monitor dopant incorporation into the emitter. This data was found to be predictive not only of the Hfe for a population, but also as an indicator of potential “renegade” Hfe behavior. INTRODUCTION Polysilicon emitters remain a vital part of many current high speed bipolar and BiCMOS production processes. In spite of their extensive and longstanding application, obtaining consistent parametric results, especially in RF applications remains a challenge. This investigation studied the influence of temperature at various points in the deposition process on bipolar parametrics. The in-situ arsenic doped polysilicon emitter layers used in this work were deposited in a vertical low pressure chemical vapor deposition (LPCVD) furnace on 200 mm wafers. Prior to loading into the furnace, wafers were wet cleaned in an HF last process that left the exposed base of the devices oxide free. Queue times between the emitter polysilicon preclean and the deposition were kept to a minimum in order to preserve the surface. The furnace construction includes a nitrogen purged transfer chamber and load-lock to prevent oxide formation during the boat push into the tube. An interfacial oxide was formed over the base region prior to the deposition of the emitter layer by introducing dilute oxygen to the furnace. The process boat containing the wafers was rotated continuously during the interfacial oxide formation and the polysilicon deposition.
One of the challenges associated with in-situ arsenic doping of polysilicon is the “poisoning” of the wafer surface by the dopant, which dramatically slows the deposition process [1]. This poisoning can lead to film thickness and parametric variations. In order to avoid this, a deposition process was
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