A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 D
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ORIGINAL RESEARCH PAPER
A memory and area‑efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real‑time image decomposition Anirban Chakraborty1 · Ayan Banerjee1 Received: 20 November 2018 / Accepted: 15 July 2019 © Springer-Verlag GmbH Germany, part of Springer Nature 2019
Abstract In this article, we have proposed the internal architecture of a dedicated hardware for 1D/2D convolution-based 9/7 and 5/3 DWT filters, exploiting bit-parallel ‘distributed arithmetic’ (DA) to reduce the computation time of our proposed DWT design while retaining the area at a comparable level to other recent existing designs. Despite using memory extensive bitparallel DA, we have successfully achieved 90% reduction in the memory size than that of the other notable architectures. Through our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, mode. With the introduction of DA, we have incorporated pipelining and parallelism into our proposed convolution-based 1D/2D DWT architectures. We have reduced the area by 38.3% and memory requirement by 90% than that of the latest remarkable designs. The critical-path delay of our design is almost 50% than that of the other latest designs. We have successfully applied our prototype 2D design for real-time image decomposition. The quality of the architecture in case of real-time image decomposition is measured by ‘peak signal-to-noise ratio’ and ‘computation time’, where our proposed design outperforms other similar kind of software- and hardware-based implementations. Keywords DWT · Distributed arithmetic · Memory efficient · Digital VLSI design · Parallelism · Image decomposition · PSNR
1 Introduction Now-a-days, ‘discrete wavelet transform’ (DWT) has gained popularity among signal-processing engineers and researchers. This is mainly because of its capability of presenting time-domain as well as frequency-domain information of a signal simultaneously [1]. Until date, various kinds of techniques have been proposed for the implementation of DWT algorithm in terms of a dedicated hardware which facilitates real-time signal processing. All these hardware implementations of DWT can be broadly classified into two heads, viz., designs based on convolution-based DWT and designs based on lifting-based DWT [2, 3]. These can again be categorized into several sub-heads. Some of the notable and * Anirban Chakraborty [email protected] 1
Electronics and Telecommunication Engineering Department, Indian Institute of Engineering Science and Technology, Shibpur, Howrah, India
recent hardware implementations of DWT are presented in the subsequent paragraphs. In the work of [4], the authors proposed two DWT architectures for 1D 9/7 DWT filters. Those architectures are based on bit-serial and bit-parallel ‘distributed arithmetic’ (DA). Though their bit-serial DA-based 1D DWT architecture of 9/7 filter requires less hardware compared to other contemporary works, the architecture is very slow and
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