A Model of Silicon Nanocrystal Nucleation and Growth on SiO 2 by CVD
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A Model of Silicon Nanocrystal Nucleation and Growth on SiO2 by CVD M.W. Stoker, T.P. Merchant, R. Rao, R. Muralidhar, S. Straub, and B.E. White Jr. Advanced Products Research and Development Laboratory, Freescale Semiconductor, Tempe, AZ 85284, U.S.A. ABSTRACT Silicon nanocrystals can be used in non-volatile memory devices to reduce susceptibility to charge loss via tunnel oxide defects, allowing scaling to smaller sizes than possible with conventional Flash memory technology. In order to optimize device performance, it is desirable to maximize the nanocrystal density and surface coverage, while maintaining sufficient intercrystallite separation to limit electron tunneling between adjacent crystallites. Ideally, crystallite densities in excess of 1012cm-2 with relatively narrow particle size distributions must be obtained, posing a significant challenge for process development and control. In order to facilitate development of such a process, a rate-expression-based model has been developed for the nucleation and growth of silicon nanocrystals on SiO2 in a CVD process. The model addresses the phenomena of nucleation, growth, and coalescence and includes the effects of exclusion zones surrounding the growing nuclei. The model uses a phenomenological expression to describe the nucleation rate and assumes that following nucleation, crystallite growth is dominated by gas-phase deposition processes, analogous to CVD of polycrystalline silicon. The model-predicted time-evolutions of crystallite densities and crystallite size distributions are consistent with experimental distributions as measured by Scanning Electron Microscopy (SEM). By coupling the model to a reactor-scale model of polysilicon CVD, it is possible to predict variations in the crystallite size distributions at various locations across a wafer as a function of reactor settings (temperature, pressure, flow rates, etc…). This in turn can be used for process control and optimization in order to ensure uniform deposition of nanocrystals in a large-scale manufacturing environment. INTRODUCTION Recently, significant attention has been focused on silicon nanocrystals for use as discretetrap storage nodes in non-volatile memory devices [1,2]. Such devices are less vulnerable to charge loss through isolated defects in the bottom oxide, and thus are expected to exhibit improved reliability and scalability compared to conventional flash memory devices based on a continuous floating gate. Furthermore, nanocrystal-based devices provide superior FowlerNordheim (FN) erase characteristics and improved data retention compared to competing discrete-trap storage technologies, such as SONOS [1]. Si nanocrystals can be deposited on a SiO2-film using chemical vapor deposition (CVD). However, optimizing the deposition process to obtain the desired nanocrystal sizes and densities is a significant challenge. In order to maximize device performance, the majority of the crystallites should be larger than 4 nm with a total crystallite density in excess of 1x1012 cm-2. Furthe
