A New Annealing Method to Obtain High Quality Poly-Si
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A NEW ANNEALING METHOD TO OBTAIN HIGH QUALITY POLY-Si YOON-HO SONG, JONG-TAE BAEK, KEE-SOO NAM, AND SANG-WON KANG Electronics and Telecommunications Research Institute, P.O. Box 8 Daedog Science Town, Daejeon, Korea ABSTRACT A new annealing method, a combination of rapid thermal annealing (RTA) and furnace annealing, has been developed to obtain a high quality poly-Si from a-Si deposited by LPCVD. This method produces a large grain poly-Si with good uniformity, which may result from the growth of relatively defect-free nucleus generated at a high temperature by RTA. Poly-Si thin film transistors fabricated by this new annealing method have higher field effect mobility and better uniformity compared with those by the conventional furnace annealing. INTRODUCTION In recent years, polycrystalline silicon thin film transistors (poly-Si TFTs) have attracted much attention for high-resolution active matrix liquid crystal displays [1] and high-density static random access memories (SRAMs) [2]. The performance of poly-Si TFTs is strongly influenced by grain boundaries and intragranular defects. Hydrogen passivation of grain boundaries [3] and crystallization (or recrystallization) of silicon films, such as solid phase crystallization (SPC) [4] and laser annealing of amorphous Si (a-Si) [5], have been extensively studied to obtain high quality poly-Si. It is necessary to enlarge grain in poly-Si for reducing grain boundary traps and to improve crystallinity of Si for reducing intragranular defects. Until now, solid phase crystallization of a-Si has been performed at a fixed low temperature (< 600 0 C) during the entire crystallization from nucleation to grain growth. This results in the large size grain but requires too long annealing time, and the grain is defective with microtwin and twin boundary [6]. In this paper, we propose a new annealing method, a combination of rapid thermal annealing (RTA) and furnace annealing to reduce the annealing time for crystallization of a-Si and obtain high quality poly-Si. Nucleation starts at a rather high temperature for a short time and then the nuclei grow at low temperature in a furnace to increase their grain size. EXPERIMENTS Amorphous silicon films of 500 A thickness were deposited on thermally oxidized 5" silicon wafers by low pressure chemical vapor deposition (LPCVD) using SiH 4 at 520 'C. These films were annealed at 750 'C for a short time in N2 by RTA apparatus and subsequently annealed at 590 'C in a N2-ambient furnace. Poly-Si films were analyzed by TEM and Raman scattering. Poly-Si TFTs were fabricated through low-temperature process, using the CVD-oxide as a gate dielectric. A 500 A thick gate oxide was deposited by LPCVD at 420 °C and Mat. Res. Soc. Symp. Proc. Vol. 283. 01993 Materials Research Society
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annealed at 590 'C in N2 ambient for 2 h. Others followed the conventional self-aligned MOS (Metal-Oxide Semiconductor) processes except for the activation of dopant. Implanted phosphorus ions were activated by thermal annealing at 590 TC for 20 h. After device fa
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